Benoit Nadeau-Dostie

Person

Gatineau, CA

People

Patents Grantslast 30 patents

Information Patent Grant
Memory built-in self-test with automated reference trim feedback fo...
- Patent number 12,046,315
- Issue date Jul 23, 2024
- SIEMENS INDUSTRY SOFTWARE INC.
- Jongsin Yun
- G11 - INFORMATION STORAGE
Information Patent Grant
Reference bits test and repair using memory built-in self-test
- Patent number 11,929,136
- Issue date Mar 12, 2024
- SIEMENS INDUSTRY SOFTWARE INC.
- Jongsin Yun
- G11 - INFORMATION STORAGE
Information Patent Grant
Asynchronous interface for transporting test-related data via seria...
- Patent number 11,789,487
- Issue date Oct 17, 2023
- SIEMENS INDUSTRY SOFTWARE INC.
- Benoit Nadeau-Dostie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable built-in self-repair chain for fast repair data loading
- Patent number 11,495,315
- Issue date Nov 8, 2022
- SIEMENS INDUSTRY SOFTWARE INC.
- Wei Zou
- G11 - INFORMATION STORAGE
Information Patent Grant
Error-correcting code-assisted memory repair
- Patent number 11,430,537
- Issue date Aug 30, 2022
- SIEMENS INDUSTRY SOFTWARE INC.
- Benoit Nadeau-Dostie
- G11 - INFORMATION STORAGE
Information Patent Grant
Test generator for low power built-in self-test
- Patent number 8,683,280
- Issue date Mar 25, 2014
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Methods for at-speed testing of memory interface
- Patent number 8,516,317
- Issue date Aug 20, 2013
- Mentor Graphics Corporation
- Benoit Nadeau-Dostie
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for storing and distributing memory repair inf...
- Patent number 7,757,135
- Issue date Jul 13, 2010
- Mentor Graphics Corporation
- Benoit Nadeau-Dostie
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for at-speed testing of memory interface using scan
- Patent number 7,617,425
- Issue date Nov 10, 2009
- LogicVision, Inc.
- Benoit Nadeau-Dostie
- G11 - INFORMATION STORAGE
Information Patent Grant
Clocking methodology for at-speed testing of scan circuits with syn...
- Patent number 7,424,656
- Issue date Sep 9, 2008
- LogicVision, Inc.
- Benoit Nadeau-Dostie
- G01 - MEASURING TESTING
Information Patent Grant
Method and circuit for collecting memory failure information
- Patent number 7,370,251
- Issue date May 6, 2008
- LogicVision, Inc.
- Benoit Nadeau-Dostie
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory repair circuit and method
- Patent number 7,257,733
- Issue date Aug 14, 2007
- LogicVision, Inc.
- Benoit Nadeau-Dostie
- G11 - INFORMATION STORAGE
Information Patent Grant
Boundary scan with strobed pad driver enable
- Patent number 7,219,282
- Issue date May 15, 2007
- LogicVision, Inc.
- Stephen K. Sunter
- G01 - MEASURING TESTING
Information Patent Grant
Method and circuit for at-speed testing of scan circuits
- Patent number 7,194,669
- Issue date Mar 20, 2007
- LogicVision, Inc.
- Benoit Nadeau-Dostie
- G01 - MEASURING TESTING
Information Patent Grant
Method of and program product for performing gate-level diagnosis o...
- Patent number 7,191,374
- Issue date Mar 13, 2007
- LogicVision, Inc.
- Fadi Maamari
- G01 - MEASURING TESTING
Information Patent Grant
Memory repair analysis method and circuit
- Patent number 7,188,274
- Issue date Mar 6, 2007
- LogicVision, Inc.
- Benoit Nadeau-Dostie
- G11 - INFORMATION STORAGE
Information Patent Grant
Clock controller for at-speed testing of scan circuits
- Patent number 7,155,651
- Issue date Dec 26, 2006
- LogicVision, Inc.
- Benoit Nadeau-Dostie
- G01 - MEASURING TESTING
Information Patent Grant
Method and test circuit for testing memory internal write enable
- Patent number 7,139,946
- Issue date Nov 21, 2006
- LogicVision, Inc.
- Benoit Nadeau-Dostie
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and program product for designing hierarchical circuit for q...
- Patent number 6,868,532
- Issue date Mar 15, 2005
- LogicVision, Inc.
- Benoit Nadeau-Dostie
- G01 - MEASURING TESTING
Information Patent Grant
Method and program product for designing hierarchical circuit for q...
- Patent number 6,862,717
- Issue date Mar 1, 2005
- LogicVision, Inc.
- Benoit Nadeau-Dostie
- G01 - MEASURING TESTING
Information Patent Grant
Method of designing circuit having multiple test access ports, circ...
- Patent number 6,829,730
- Issue date Dec 7, 2004
- LogicVision, Inc.
- Benoit Nadeau-Dostie
- G01 - MEASURING TESTING
Information Patent Grant
Method for scan testing of digital circuit, digital circuit for use...
- Patent number 6,763,489
- Issue date Jul 13, 2004
- LogicVision, Inc.
- Benoit Nadeau-Dostie
- G01 - MEASURING TESTING
Information Patent Grant
Test access circuit and method of accessing embedded test controlle...
- Patent number 6,760,874
- Issue date Jul 6, 2004
- LogicVision, Inc.
- Jean-Francois Côté
- G01 - MEASURING TESTING
Information Patent Grant
Method of masking corrupt bits during signature analysis and circui...
- Patent number 6,745,359
- Issue date Jun 1, 2004
- LogicVision, Inc.
- Benoit Nadeau-Dostie
- G01 - MEASURING TESTING
Information Patent Grant
Method for collecting failure information for a memory using an emb...
- Patent number 6,738,938
- Issue date May 18, 2004
- LogicVision, Inc.
- Benoit Nadeau-Dostie
- G11 - INFORMATION STORAGE
Information Patent Grant
Scan test method for providing real time identification of failing...
- Patent number 6,671,839
- Issue date Dec 30, 2003
- LogicVision, Inc.
- Jean-Francois Côté
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and circuitry for controlling clocks of embedded blocks duri...
- Patent number 6,614,263
- Issue date Sep 2, 2003
- LogicVision, Inc.
- Benoit Nadeau-Dostie
- G01 - MEASURING TESTING
Information Patent Grant
Hierarchical design and test method and system, program product emb...
- Patent number 6,615,392
- Issue date Sep 2, 2003
- LogicVision, Inc.
- Benoit Nadeau-Dostie
- G01 - MEASURING TESTING
Information Patent Grant
Fault insertion method, boundary scan cells, and integrated circuit...
- Patent number 6,536,008
- Issue date Mar 18, 2003
- Logic Vision, Inc.
- Benoit Nadeau-Dostie
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for testing high performance circuits
- Patent number 6,510,534
- Issue date Jan 21, 2003
- LogicVision, Inc.
- Benoit Nadeau-Dostie
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
NON-DESTRUCTIVE MEMORY SELF-TEST
- Publication number 20250157560
- Publication date May 15, 2025
- Siemens Industry Software Inc.
- Benoit Nadeau-Dostie
- G11 - INFORMATION STORAGE
Information Patent Application
READ-ONLY MEMORY DIAGNOSIS AND REPAIR
- Publication number 20240087665
- Publication date Mar 14, 2024
- Siemens Industry Software Inc.
- Benoit Nadeau-Dostie
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY BUILT-IN SELF-TEST WITH AUTOMATED REFERENCE TRIM FEEDBACK FO...
- Publication number 20240013846
- Publication date Jan 11, 2024
- Siemens Industry Software Inc.
- Jongsin Yun
- G11 - INFORMATION STORAGE
Information Patent Application
REFERENCE BITS TEST AND REPAIR USING MEMORY BUILT-IN SELF-TEST
- Publication number 20230178172
- Publication date Jun 8, 2023
- Siemens Industry Software Inc.
- Jongsin Yun
- G11 - INFORMATION STORAGE
Information Patent Application
ASYNCHRONOUS INTERFACE FOR TRANSPORTING TEST-RELATED DATA VIA SERIA...
- Publication number 20230110161
- Publication date Apr 13, 2023
- Siemens Industry Software Inc.
- Benoit Nadeau-Dostie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR PROCESSING MEMORY REPAIR INFORMATION
- Publication number 20220215896
- Publication date Jul 7, 2022
- Siemens Industry Software Inc.
- Benoit Nadeau-Dostie
- G11 - INFORMATION STORAGE
Information Patent Application
Error-Correcting Code-Assisted Memory Repair
- Publication number 20210174892
- Publication date Jun 10, 2021
- Mentor Graphics Corporation
- Benoit Nadeau-Dostie
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD FOR AT-SPEED TESTING OF MEMORY INTERFACE USING SCAN
- Publication number 20100037109
- Publication date Feb 11, 2010
- LogicVision, Inc.
- Benoit Nadeau-Dostie
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR STORING AND DISTRIBUTING MEMORY REPAIR INF...
- Publication number 20080065929
- Publication date Mar 13, 2008
- LogicVision, Inc.
- Benoit NADEAU-DOSTIE
- G11 - INFORMATION STORAGE
Information Patent Application
Method for at-speed testing of memory interface using scan
- Publication number 20070266278
- Publication date Nov 15, 2007
- Benoit Nadeau-Dostie
- G11 - INFORMATION STORAGE
Information Patent Application
Insertion of embedded test in RTL to GDSII flow
- Publication number 20050273683
- Publication date Dec 8, 2005
- LogicVision, Inc.
- Jean-Francois Cote
- G01 - MEASURING TESTING
Information Patent Application
Clocking methodology for at-speed testing of scan circuits with syn...
- Publication number 20050240790
- Publication date Oct 27, 2005
- LogicVision, Inc.
- Benoit Nadeau-Dostie
- G01 - MEASURING TESTING
Information Patent Application
Masking circuit and method of masking corrupted bits
- Publication number 20050240848
- Publication date Oct 27, 2005
- LogicVision, Inc.
- Jean-Francois Cote
- G01 - MEASURING TESTING
Information Patent Application
Clock controller for at-speed testing of scan circuits
- Publication number 20050240847
- Publication date Oct 27, 2005
- LogicVision, Inc.
- Benoit Nadeau-Dostie
- G01 - MEASURING TESTING
Information Patent Application
Method and circuit for collecting memory failure information
- Publication number 20050047229
- Publication date Mar 3, 2005
- Benoit Nadeau-Dostie
- G11 - INFORMATION STORAGE
Information Patent Application
Processor interface for test access port
- Publication number 20050028059
- Publication date Feb 3, 2005
- Jean-Francois Cote
- G01 - MEASURING TESTING
Information Patent Application
Memory repair circuit and method
- Publication number 20040257901
- Publication date Dec 23, 2004
- Benoit Nadeau-Dostie
- G11 - INFORMATION STORAGE
Information Patent Application
Method and circuit for at-speed testing of scan circuits
- Publication number 20040163021
- Publication date Aug 19, 2004
- Benoit Nadeau-Dostie
- G01 - MEASURING TESTING
Information Patent Application
Memory repair analysis method and circuit
- Publication number 20040163015
- Publication date Aug 19, 2004
- Benoit Nadeau-Dostie
- G11 - INFORMATION STORAGE
Information Patent Application
Method and test circuit for testing memory internal write enable
- Publication number 20040123203
- Publication date Jun 24, 2004
- Benoit Nadeau-Dostie
- G11 - INFORMATION STORAGE
Information Patent Application
Boundary scan with strobed pad driver enable
- Publication number 20040098648
- Publication date May 20, 2004
- Stephen K. Sunter
- G01 - MEASURING TESTING
Information Patent Application
SCAN TEST METHOD FOR PROVIDING REAL TIME IDENTIFICATION OF FAILING...
- Publication number 20040003329
- Publication date Jan 1, 2004
- Jean-Francois Cote
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of masking corrupt bits during signature analysis and circui...
- Publication number 20030229833
- Publication date Dec 11, 2003
- Benoit Nadeau-Dostie
- G01 - MEASURING TESTING
Information Patent Application
Method for collecting failure information for a memory using an emb...
- Publication number 20030226073
- Publication date Dec 4, 2003
- Benoit Nadeau-Dostie
- G11 - INFORMATION STORAGE
Information Patent Application
Method of and program product for performing gate-level diagnosis o...
- Publication number 20030217315
- Publication date Nov 20, 2003
- Fadi Maamari
- G01 - MEASURING TESTING
Information Patent Application
Test access circuit and method of accessing embedded test controlle...
- Publication number 20030212524
- Publication date Nov 13, 2003
- Jean-Francois Cote
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND CIRCUITRY FOR CONTROLLING CLOCKS OF EMBEDDED BLOCKS DURI...
- Publication number 20030146777
- Publication date Aug 7, 2003
- Benoit Nadeau-Dostie
- G01 - MEASURING TESTING
Information Patent Application
Method and program product for designing hierarchical circuit for q...
- Publication number 20030115522
- Publication date Jun 19, 2003
- Benoit Nadeau-Dostie
- G01 - MEASURING TESTING
Information Patent Application
Method and program product for designing hierarchical circuit for q...
- Publication number 20030110457
- Publication date Jun 12, 2003
- Benoit Nadeau-Dostie
- G01 - MEASURING TESTING
Information Patent Application
Method of designing circuit having multiple test access ports, circ...
- Publication number 20020184562
- Publication date Dec 5, 2002
- Benoit Nadeau-Dostie
- G01 - MEASURING TESTING

Benoit Nadeau-Dostie

Person

Patents Grantslast 30 patents

Memory built-in self-test with automated reference trim feedback fo...

Reference bits test and repair using memory built-in self-test

Asynchronous interface for transporting test-related data via seria...

Configurable built-in self-repair chain for fast repair data loading

Error-correcting code-assisted memory repair

Test generator for low power built-in self-test

Methods for at-speed testing of memory interface

Method and apparatus for storing and distributing memory repair inf...

Method for at-speed testing of memory interface using scan

Clocking methodology for at-speed testing of scan circuits with syn...

Method and circuit for collecting memory failure information

Memory repair circuit and method

Boundary scan with strobed pad driver enable

Method and circuit for at-speed testing of scan circuits

Method of and program product for performing gate-level diagnosis o...

Memory repair analysis method and circuit

Clock controller for at-speed testing of scan circuits

Method and test circuit for testing memory internal write enable

Method and program product for designing hierarchical circuit for q...

Method and program product for designing hierarchical circuit for q...

Method of designing circuit having multiple test access ports, circ...

Method for scan testing of digital circuit, digital circuit for use...

Test access circuit and method of accessing embedded test controlle...

Method of masking corrupt bits during signature analysis and circui...

Method for collecting failure information for a memory using an emb...

Scan test method for providing real time identification of failing...

Method and circuitry for controlling clocks of embedded blocks duri...

Hierarchical design and test method and system, program product emb...

Fault insertion method, boundary scan cells, and integrated circuit...

Method and apparatus for testing high performance circuits

Patents Applicationslast 30 patents

NON-DESTRUCTIVE MEMORY SELF-TEST

READ-ONLY MEMORY DIAGNOSIS AND REPAIR

MEMORY BUILT-IN SELF-TEST WITH AUTOMATED REFERENCE TRIM FEEDBACK FO...

REFERENCE BITS TEST AND REPAIR USING MEMORY BUILT-IN SELF-TEST

ASYNCHRONOUS INTERFACE FOR TRANSPORTING TEST-RELATED DATA VIA SERIA...

METHOD AND APPARATUS FOR PROCESSING MEMORY REPAIR INFORMATION

Error-Correcting Code-Assisted Memory Repair

METHOD FOR AT-SPEED TESTING OF MEMORY INTERFACE USING SCAN

METHOD AND APPARATUS FOR STORING AND DISTRIBUTING MEMORY REPAIR INF...

Method for at-speed testing of memory interface using scan

Insertion of embedded test in RTL to GDSII flow

Clocking methodology for at-speed testing of scan circuits with syn...

Masking circuit and method of masking corrupted bits

Clock controller for at-speed testing of scan circuits

Method and circuit for collecting memory failure information

Processor interface for test access port

Memory repair circuit and method

Method and circuit for at-speed testing of scan circuits

Memory repair analysis method and circuit

Method and test circuit for testing memory internal write enable

Boundary scan with strobed pad driver enable

SCAN TEST METHOD FOR PROVIDING REAL TIME IDENTIFICATION OF FAILING...

Method of masking corrupt bits during signature analysis and circui...

Method for collecting failure information for a memory using an emb...

Method of and program product for performing gate-level diagnosis o...

Test access circuit and method of accessing embedded test controlle...

METHOD AND CIRCUITRY FOR CONTROLLING CLOCKS OF EMBEDDED BLOCKS DURI...

Method and program product for designing hierarchical circuit for q...

Method and program product for designing hierarchical circuit for q...

Method of designing circuit having multiple test access ports, circ...