Bhavesh G. Bhakta

Person

Richardson, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methods and apparatus to retime data using a programmable delay
- Patent number 12,028,079
- Issue date Jul 2, 2024
- Texas Instruments Incorporated
- Bhavesh G. Bhakta
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low power loss of lock detector
- Patent number 9,503,104
- Issue date Nov 22, 2016
- Texas Instruments Incorporated
- Mustafa Ulvi Erdogan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Electronic device and method for buffering
- Patent number 8,653,856
- Issue date Feb 18, 2014
- Texas Instruments Incorporated
- Oliver Piepenstock
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High performance LVDS driver for scalable supply
- Patent number 7,944,252
- Issue date May 17, 2011
- Texas Instruments Incorporated
- Bhavesh G. Bhakta
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Circuit and method for evaluating the performance of an adaptive de...
- Patent number 7,782,932
- Issue date Aug 24, 2010
- Texas Instruments Incorporated
- Robert F. Payne
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Hybrid analog to digital converter circuit and method
- Patent number 7,733,261
- Issue date Jun 8, 2010
- Texas Instruments Incorporated
- Bhavesh Bhakta
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
High speed decision feedback equalizer
- Patent number 7,443,913
- Issue date Oct 28, 2008
- Texas Instruments Incorporated
- Bhavesh G. Bhakta
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
High performance FIR filter
- Patent number 7,349,932
- Issue date Mar 25, 2008
- Texas Instruments Incorporated
- Bhavesh G. Bhakta
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit to observe internal clock and control signals in a receiver...
- Patent number 7,315,182
- Issue date Jan 1, 2008
- Texas Instruments Incorporated
- Robert Floyd Payne
- G01 - MEASURING TESTING
Information Patent Grant
Methodology for designing high speed receivers below a target bit-e...
- Patent number 7,277,828
- Issue date Oct 2, 2007
- Texas Instruments Incorporated
- Sridhar Ramaswamy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Implementation method of digital phase-locked loop
- Patent number 6,813,111
- Issue date Nov 2, 2004
- Texas Instruments Incorporated
- Bhavesh G. Bhakta
- G11 - INFORMATION STORAGE
Information Patent Grant
Decision error compensation technique for decision-directed timing...
- Patent number 6,738,206
- Issue date May 18, 2004
- Texas Instruments Incorporated
- Younggyun Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Decimated digital phase-locked loop for high-speed implementation
- Patent number 6,636,120
- Issue date Oct 21, 2003
- Texas Instruments Incorporated
- Bhavesh G. Bhakta
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and circuit for dibit detection
- Patent number 6,256,159
- Issue date Jul 3, 2001
- Texas Instruments Incorporated
- Bhavesh G. Bhakta
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
METHODS AND APPARATUS TO RETIME DATA USING A PROGRAMMABLE DELAY
- Publication number 20240313786
- Publication date Sep 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Bhavesh G. Bhakta
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD AND CIRCUIT FOR DLL LOCKING MECHANISM FOR WIDE RANGE HARMONI...
- Publication number 20240146315
- Publication date May 2, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Venkateswara Pothireddy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHODS AND APPARATUS TO RETIME DATA USING A PROGRAMMABLE DELAY
- Publication number 20230378961
- Publication date Nov 23, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Bhavesh G. Bhakta
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CLOCK RECOVERY TRAINING
- Publication number 20220407674
- Publication date Dec 22, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Bhavesh BHAKTA
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
CURRENT MIRROR WITH DEPLETION MODE MOS AND EMBEDDED NOISE FILTER
- Publication number 20160048152
- Publication date Feb 18, 2016
- TEXAS INSTRUMENTS INCORPORATED
- Bhavesh G. Bhakta
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOW POWER LOSS OF LOCK DETECTOR
- Publication number 20150365094
- Publication date Dec 17, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Mustafa Ulvi ERDOGAN
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
ELECTRONIC DEVICE AND METHOD FOR BUFFERING
- Publication number 20120074987
- Publication date Mar 29, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Oliver Piepenstock
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
EFFICIENT RETIMER FOR CLOCK DIVIDERS
- Publication number 20110193598
- Publication date Aug 11, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Bhavesh G. Bhakta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMACE LVDS DRIVER FOR SCALABLE SUPPLY
- Publication number 20110102083
- Publication date May 5, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Bhavesh G. Bhakta
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Hybrid Analog to Digital Converter Circuit and Method
- Publication number 20100066574
- Publication date Mar 18, 2010
- TEXAS INSTRUMENTS INCORPORATED
- Bhavesh BHAKTA
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
Circuit to observe internal clock and control signals in a receiver...
- Publication number 20050249295
- Publication date Nov 10, 2005
- Robert Floyd Payne
- G01 - MEASURING TESTING
Information Patent Application
Circuit and method for evaluating the performance of an adaptive de...
- Publication number 20050238093
- Publication date Oct 27, 2005
- TEXAS INSTRUMENTS INCORPORATED
- Robert F. Payne
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Built-in self test method and apparatus for jitter transfer, jitter...
- Publication number 20050193290
- Publication date Sep 1, 2005
- James B. Cho
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
High speed decision feedback equalizer
- Publication number 20050180498
- Publication date Aug 18, 2005
- TEXAS INSTRUMENTS INCORPORATED
- Bhavesh G. Bhakta
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
High performance FIR filter
- Publication number 20050182805
- Publication date Aug 18, 2005
- TEXAS INSTRUMENTS INCORPORATED
- Bhavesh G. Bhakta
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Methodology for designing high speed receivers below a target bit-e...
- Publication number 20050182807
- Publication date Aug 18, 2005
- TEXAS INSTRUMENTS INCORPORATED
- Sridhar Ramaswamy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
High performance sense amplifiers
- Publication number 20050162193
- Publication date Jul 28, 2005
- TEXAS INSTRUMENTS INCORPORATED
- Robert F. Payne
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Fixed decision delay detectors for timing recovery loop
- Publication number 20020172305
- Publication date Nov 21, 2002
- Younggyun Kim
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Timing recovery loop latency reduction via loop filter pre-calculation
- Publication number 20020141089
- Publication date Oct 3, 2002
- Younggyun Kim
- G11 - INFORMATION STORAGE
Information Patent Application
Implementation method of digital phase-locked loop
- Publication number 20020080516
- Publication date Jun 27, 2002
- Bhavesh G. Bhakta
- G11 - INFORMATION STORAGE
Information Patent Application
Decimated digital phase-locked loop for high-speed implementation
- Publication number 20020075078
- Publication date Jun 20, 2002
- Bhavesh G. Bhakta
- G11 - INFORMATION STORAGE
Information Patent Application
Decision error compensation technique for decision-directed timing...
- Publication number 20020063982
- Publication date May 30, 2002
- Younggyun Kim
- G11 - INFORMATION STORAGE

Bhavesh G. Bhakta

Person

Patents Grantslast 30 patents

Methods and apparatus to retime data using a programmable delay

Low power loss of lock detector

Electronic device and method for buffering

High performance LVDS driver for scalable supply

Circuit and method for evaluating the performance of an adaptive de...

Hybrid analog to digital converter circuit and method

High speed decision feedback equalizer

High performance FIR filter

Circuit to observe internal clock and control signals in a receiver...

Methodology for designing high speed receivers below a target bit-e...

Implementation method of digital phase-locked loop

Decision error compensation technique for decision-directed timing...

Decimated digital phase-locked loop for high-speed implementation

Method and circuit for dibit detection

Patents Applicationslast 30 patents

METHODS AND APPARATUS TO RETIME DATA USING A PROGRAMMABLE DELAY

METHOD AND CIRCUIT FOR DLL LOCKING MECHANISM FOR WIDE RANGE HARMONI...

METHODS AND APPARATUS TO RETIME DATA USING A PROGRAMMABLE DELAY

CLOCK RECOVERY TRAINING

CURRENT MIRROR WITH DEPLETION MODE MOS AND EMBEDDED NOISE FILTER

LOW POWER LOSS OF LOCK DETECTOR

ELECTRONIC DEVICE AND METHOD FOR BUFFERING

EFFICIENT RETIMER FOR CLOCK DIVIDERS

HIGH PERFORMACE LVDS DRIVER FOR SCALABLE SUPPLY

Hybrid Analog to Digital Converter Circuit and Method

Circuit to observe internal clock and control signals in a receiver...

Circuit and method for evaluating the performance of an adaptive de...

Built-in self test method and apparatus for jitter transfer, jitter...

High speed decision feedback equalizer

High performance FIR filter

Methodology for designing high speed receivers below a target bit-e...

High performance sense amplifiers

Fixed decision delay detectors for timing recovery loop

Timing recovery loop latency reduction via loop filter pre-calculation

Implementation method of digital phase-locked loop

Decimated digital phase-locked loop for high-speed implementation

Decision error compensation technique for decision-directed timing...