Bill Nale

Person

Livermore, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatus, system and method to detect and improve an input clock p...
- Patent number 12,217,787
- Issue date Feb 4, 2025
- Intel Corporation
- Arvind A. Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance interconnect
- Patent number 12,197,357
- Issue date Jan 14, 2025
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance interconnect
- Patent number 12,189,550
- Issue date Jan 7, 2025
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic random access memory built-in self-test power fail mitigation
- Patent number 12,190,979
- Issue date Jan 7, 2025
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory chip with per row activation count having error correction c...
- Patent number 12,164,373
- Issue date Dec 10, 2024
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance memory module with reduced loading
- Patent number 12,147,698
- Issue date Nov 19, 2024
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power control of a memory device in connected standby state
- Patent number 12,106,818
- Issue date Oct 1, 2024
- Intel Corporation
- Aiswarya M. Pious
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Refresh command control for host assist of row hammer mitigation
- Patent number 11,990,172
- Issue date May 21, 2024
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Undo and redo of soft post package repair
- Patent number 11,837,314
- Issue date Dec 5, 2023
- SK Hynix NAND Product Solutions Corp.
- Bill Nale
- G11 - INFORMATION STORAGE
Information Patent Grant
Periodic calibrations during memory device self refresh
- Patent number 11,790,976
- Issue date Oct 17, 2023
- Intel Corporation
- Christopher E. Cox
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance interconnect
- Patent number 11,741,030
- Issue date Aug 29, 2023
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synchronous dynamic random access memory (SDRAM) dual in-line memor...
- Patent number 11,699,471
- Issue date Jul 11, 2023
- Intel Corporation
- Duane E. Galbi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Refresh command control for host assist of row hammer mitigation
- Patent number 11,688,452
- Issue date Jun 27, 2023
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Applying chip select for memory device identification and power man...
- Patent number 11,335,395
- Issue date May 17, 2022
- Intel Corporation
- Christopher E. Cox
- G11 - INFORMATION STORAGE
Information Patent Grant
Refresh command control for host assist of row hammer mitigation
- Patent number 11,282,561
- Issue date Mar 22, 2022
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Periodic calibrations during memory device self refresh
- Patent number 11,276,453
- Issue date Mar 15, 2022
- Intel Corporation
- Christopher E. Cox
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance interconnect
- Patent number 11,269,793
- Issue date Mar 8, 2022
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enumerated per device addressability for memory subsystems
- Patent number 10,997,096
- Issue date May 4, 2021
- Intel Corporation
- Tonia G. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller that filters a count of row activate commands col...
- Patent number 10,969,997
- Issue date Apr 6, 2021
- Intel Corporation
- William Nale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High bandwidth DIMM
- Patent number 10,963,404
- Issue date Mar 30, 2021
- Intel Corporation
- James A. McCall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Refresh command control for host assist of row hammer mitigation
- Patent number 10,950,288
- Issue date Mar 16, 2021
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques to store data for critical chunk operations
- Patent number 10,884,941
- Issue date Jan 5, 2021
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DIMM for a high bandwidth memory channel
- Patent number 10,884,958
- Issue date Jan 5, 2021
- Intel Corporation
- Rajat Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Internal error checking and correction (ECC) with extra system bits
- Patent number 10,872,011
- Issue date Dec 22, 2020
- Intel Corporation
- Kuljit S. Bains
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Applying chip select for memory device identification and power man...
- Patent number 10,839,887
- Issue date Nov 17, 2020
- Intel Corporation
- Christopher E. Cox
- G11 - INFORMATION STORAGE
Information Patent Grant
Per row activation count values embedded in storage cell array stor...
- Patent number 10,825,534
- Issue date Nov 3, 2020
- Intel Corporation
- William Nale
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory control management of a processor
- Patent number 10,810,141
- Issue date Oct 20, 2020
- Intel Corporation
- Mahesh S. Natu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques to mirror a command/address or interpret command/address...
- Patent number 10,802,532
- Issue date Oct 13, 2020
- Intel Corporation
- George Vergis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing error handling operations using...
- Patent number 10,795,755
- Issue date Oct 6, 2020
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for setting high address bits in a memory module
- Patent number 10,783,028
- Issue date Sep 22, 2020
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MEMORY CHIP WITH PER ROW ACTIVATION COUNT HAVING ERROR CORRECTION C...
- Publication number 20250077352
- Publication date Mar 6, 2025
- Intel Corporation
- Bill NALE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC RANDOM ACCESS MEMORY BUILT-IN SELF-TEST POWER FAIL MITIGATION
- Publication number 20240021263
- Publication date Jan 18, 2024
- Intel Corporation
- Bill NALE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE INTERCONNECT
- Publication number 20240012772
- Publication date Jan 11, 2024
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REFRESH COMMAND CONTROL FOR HOST ASSIST OF ROW HAMMER MITIGATION
- Publication number 20230386548
- Publication date Nov 30, 2023
- Intel Corporation
- Bill NALE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLEXED RANKS (MR) WITH PSEUDO BURST LENGTH 32 (BL32)
- Publication number 20230071117
- Publication date Mar 9, 2023
- Intel Corporation
- Hussein ALAMEER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RANDOMIZATION OF DIRECTED REFRESH MANAGEMENT (DRFM) PSEUDO TARGET R...
- Publication number 20220293162
- Publication date Sep 15, 2022
- Intel Corporation
- Bill NALE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF POLLING ROW HAMMER (RH) INDICATOR INSIDE MEMORY
- Publication number 20220262428
- Publication date Aug 18, 2022
- Intel Corporation
- Kuljit S. BAINS
- G11 - INFORMATION STORAGE
Information Patent Application
BUFFER COMMUNICATION FOR DATA BUFFERS SUPPORTING MULTIPLE PSEUDO CH...
- Publication number 20220229790
- Publication date Jul 21, 2022
- Intel Corporation
- Bill NALE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REFRESH COMMAND CONTROL FOR HOST ASSIST OF ROW HAMMER MITIGATION
- Publication number 20220189532
- Publication date Jun 16, 2022
- Intel Corporation
- Bill NALE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERIODIC CALIBRATIONS DURING MEMORY DEVICE SELF REFRESH
- Publication number 20220157374
- Publication date May 19, 2022
- Intel Corporation
- Christopher E. COX
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERFECT ROW HAMMER TRACKING WITH MULTIPLE COUNT INCREMENTS
- Publication number 20220121398
- Publication date Apr 21, 2022
- Intel Corporation
- Bill NALE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE INTERCONNECT
- Publication number 20220114122
- Publication date Apr 14, 2022
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CHIP WITH PER ROW ACTIVATION COUNT HAVING ERROR CORRECTION C...
- Publication number 20210365316
- Publication date Nov 25, 2021
- Intel Corporation
- Bill NALE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY BUS INTEGRITY AND DATA ENCRYPTION (IDE)
- Publication number 20210336767
- Publication date Oct 28, 2021
- Intel Corporation
- Raghunandan MAKARAM
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
APPARATUS, SYSTEM AND METHOD TO DETECT AND IMPROVE AN INPUT CLOCK P...
- Publication number 20210312972
- Publication date Oct 7, 2021
- Arvind A. Kumar
- G11 - INFORMATION STORAGE
Information Patent Application
DOUBLE FETCH FOR LONG BURST LENGTH MEMORY DATA TRANSFER
- Publication number 20210286561
- Publication date Sep 16, 2021
- Intel Corporation
- Kuljit S. BAINS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUFFER THAT SUPPORTS BURST TRANSFERS HAVING PARALLEL CRC AND DATA T...
- Publication number 20210279128
- Publication date Sep 9, 2021
- Intel Corporation
- James A. McCALL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR MEMORY CHIP ROW HAMMER THREAT BACKPRESSURE...
- Publication number 20210264999
- Publication date Aug 26, 2021
- Intel Corporation
- Kuljit S. BAINS
- G11 - INFORMATION STORAGE
Information Patent Application
HIGH PERFORMANCE MEMORY MODULE WITH REDUCED LOADING
- Publication number 20210216238
- Publication date Jul 15, 2021
- Intel Corporation
- Bill NALE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REFRESH COMMAND CONTROL FOR HOST ASSIST OF ROW HAMMER MITIGATION
- Publication number 20210151095
- Publication date May 20, 2021
- Intel Corporation
- Bill NALE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER CONTROL OF A MEMORY DEVICE IN CONNECTED STANDBY STATE
- Publication number 20210151083
- Publication date May 20, 2021
- Intel Corporation
- Aiswarya M. PIOUS
- G11 - INFORMATION STORAGE
Information Patent Application
DISTRIBUTION OF ERROR CHECKING AND CORRECTION (ECC) BITS TO ALLOCAT...
- Publication number 20210141692
- Publication date May 13, 2021
- Intel Corporation
- Rajat AGARWAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE INTERCONNECT
- Publication number 20210117350
- Publication date Apr 22, 2021
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPLYING CHIP SELECT FOR MEMORY DEVICE IDENTIFICATION AND POWER MAN...
- Publication number 20210020224
- Publication date Jan 21, 2021
- Intel Corporation
- Christopher E. COX
- G11 - INFORMATION STORAGE
Information Patent Application
PERIODIC CALIBRATIONS DURING MEMORY DEVICE SELF REFRESH
- Publication number 20210005245
- Publication date Jan 7, 2021
- Intel Corporation
- Christopher E. COX
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY (SDRAM) DUAL IN-LINE MEMOR...
- Publication number 20210005234
- Publication date Jan 7, 2021
- Intel Corporation
- Duane E. GALBI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE INTERCONNECT
- Publication number 20200356502
- Publication date Nov 12, 2020
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UNDO AND REDO OF SOFT POST PACKAGE REPAIR
- Publication number 20200185052
- Publication date Jun 11, 2020
- Intel Corporation
- Bill Nale
- G11 - INFORMATION STORAGE
Information Patent Application
DYNAMIC RANDOM ACCESS MEMORY BUILT-IN SELF-TEST POWER FAIL MITIGATION
- Publication number 20200176072
- Publication date Jun 4, 2020
- Intel Corporation
- Bill NALE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPLYING CHIP SELECT FOR MEMORY DEVICE IDENTIFICATION AND POWER MAN...
- Publication number 20190392886
- Publication date Dec 26, 2019
- Intel Corporation
- Christopher E. COX
- G11 - INFORMATION STORAGE

Person

Patents Grantslast 30 patents

Apparatus, system and method to detect and improve an input clock p...

High performance interconnect

High performance interconnect

Dynamic random access memory built-in self-test power fail mitigation

Memory chip with per row activation count having error correction c...

High performance memory module with reduced loading

Power control of a memory device in connected standby state

Refresh command control for host assist of row hammer mitigation

Undo and redo of soft post package repair

Periodic calibrations during memory device self refresh

High performance interconnect

Synchronous dynamic random access memory (SDRAM) dual in-line memor...

Refresh command control for host assist of row hammer mitigation

Applying chip select for memory device identification and power man...

Refresh command control for host assist of row hammer mitigation

Periodic calibrations during memory device self refresh

High performance interconnect

Enumerated per device addressability for memory subsystems

Memory controller that filters a count of row activate commands col...

High bandwidth DIMM

Refresh command control for host assist of row hammer mitigation

Techniques to store data for critical chunk operations

DIMM for a high bandwidth memory channel

Internal error checking and correction (ECC) with extra system bits

Applying chip select for memory device identification and power man...

Per row activation count values embedded in storage cell array stor...

Memory control management of a processor

Techniques to mirror a command/address or interpret command/address...

Method and apparatus for performing error handling operations using...

Method and apparatus for setting high address bits in a memory module

Patents Applicationslast 30 patents

MEMORY CHIP WITH PER ROW ACTIVATION COUNT HAVING ERROR CORRECTION C...

DYNAMIC RANDOM ACCESS MEMORY BUILT-IN SELF-TEST POWER FAIL MITIGATION

HIGH PERFORMANCE INTERCONNECT

REFRESH COMMAND CONTROL FOR HOST ASSIST OF ROW HAMMER MITIGATION

MULTIPLEXED RANKS (MR) WITH PSEUDO BURST LENGTH 32 (BL32)

RANDOMIZATION OF DIRECTED REFRESH MANAGEMENT (DRFM) PSEUDO TARGET R...

METHOD OF POLLING ROW HAMMER (RH) INDICATOR INSIDE MEMORY

BUFFER COMMUNICATION FOR DATA BUFFERS SUPPORTING MULTIPLE PSEUDO CH...

REFRESH COMMAND CONTROL FOR HOST ASSIST OF ROW HAMMER MITIGATION

PERIODIC CALIBRATIONS DURING MEMORY DEVICE SELF REFRESH

PERFECT ROW HAMMER TRACKING WITH MULTIPLE COUNT INCREMENTS

HIGH PERFORMANCE INTERCONNECT

MEMORY CHIP WITH PER ROW ACTIVATION COUNT HAVING ERROR CORRECTION C...

MEMORY BUS INTEGRITY AND DATA ENCRYPTION (IDE)

APPARATUS, SYSTEM AND METHOD TO DETECT AND IMPROVE AN INPUT CLOCK P...

DOUBLE FETCH FOR LONG BURST LENGTH MEMORY DATA TRANSFER

BUFFER THAT SUPPORTS BURST TRANSFERS HAVING PARALLEL CRC AND DATA T...

METHOD AND APPARATUS FOR MEMORY CHIP ROW HAMMER THREAT BACKPRESSURE...

HIGH PERFORMANCE MEMORY MODULE WITH REDUCED LOADING

REFRESH COMMAND CONTROL FOR HOST ASSIST OF ROW HAMMER MITIGATION

POWER CONTROL OF A MEMORY DEVICE IN CONNECTED STANDBY STATE

DISTRIBUTION OF ERROR CHECKING AND CORRECTION (ECC) BITS TO ALLOCAT...

HIGH PERFORMANCE INTERCONNECT

APPLYING CHIP SELECT FOR MEMORY DEVICE IDENTIFICATION AND POWER MAN...

PERIODIC CALIBRATIONS DURING MEMORY DEVICE SELF REFRESH

SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY (SDRAM) DUAL IN-LINE MEMOR...

HIGH PERFORMANCE INTERCONNECT

UNDO AND REDO OF SOFT POST PACKAGE REPAIR

DYNAMIC RANDOM ACCESS MEMORY BUILT-IN SELF-TEST POWER FAIL MITIGATION

APPLYING CHIP SELECT FOR MEMORY DEVICE IDENTIFICATION AND POWER MAN...