Birendra Nath Agarwala

Person

Hopewell Juction, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method of forming metal interconnect structures in ultra low-k diel...
- Patent number 8,466,056
- Issue date Jun 18, 2013
- International Business Machines Corporation
- Birendra Agarwala
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure for modeling stress-induced degradation of conductive int...
- Patent number 7,692,439
- Issue date Apr 6, 2010
- International Business Machines Corporation
- Kaushik Chanda
- G01 - MEASURING TESTING
Information Patent Grant
Structure for monitoring stress-induced degradation of conductive i...
- Patent number 7,639,032
- Issue date Dec 29, 2009
- International Business Machines Corporation
- Kaushik Chanda
- G01 - MEASURING TESTING
Information Patent Grant
Dual damascene multi-level metallization
- Patent number 7,470,613
- Issue date Dec 30, 2008
- International Business Machines Corporation
- Birendra N. Agarwala
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method for monitoring stress-induced degradation of c...
- Patent number 7,397,260
- Issue date Jul 8, 2008
- International Business Machines Corporation
- Kaushik Chanda
- G01 - MEASURING TESTING
Information Patent Grant
Process for forming a redundant structure
- Patent number 7,279,411
- Issue date Oct 9, 2007
- International Business Machines Corporation
- Birendra N. Agarwala
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual-damascene metallization interconnection
- Patent number 7,224,063
- Issue date May 29, 2007
- International Business Machines Corporation
- Birendra N. Agarwala
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Edge seal for a semiconductor device
- Patent number 7,163,883
- Issue date Jan 16, 2007
- International Business Machines Corporation
- Birendra N. Agarwala
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Via barrier layers continuous with metal line barrier layers at not...
- Patent number 7,138,714
- Issue date Nov 21, 2006
- International Business Machines Corporation
- Du B. Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked via-stud with improved reliability in copper metallurgy
- Patent number 6,972,209
- Issue date Dec 6, 2005
- International Business Machines Corporation
- Birendra N. Agarwala
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method for eliminating time dependent dielectric brea...
- Patent number 6,825,561
- Issue date Nov 30, 2004
- International Business Machines Corporation
- Birendra N. Agarwala
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making an edge seal for a semiconductor device
- Patent number 6,734,090
- Issue date May 11, 2004
- International Business Machines Corporation
- Birendra N. Agarwala
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wire interconnect structure for electrically and mechanically conne...
- Patent number 6,271,599
- Issue date Aug 7, 2001
- International Business Machines Corporation
- Birendra N. Agarwala
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ball limiting metalization process for interconnection
- Patent number 6,111,321
- Issue date Aug 29, 2000
- International Business Machines Corporation
- Birendra Nath Agarwala
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for providing electrically fusible links in copper interconn...
- Patent number 6,033,939
- Issue date Mar 7, 2000
- International Business Machines Corporation
- Birendra N. Agarwala
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process of making pad structure for solder ball limiting metallurgy...
- Patent number 5,376,584
- Issue date Dec 27, 1994
- International Business Machines Corporation
- Birendra N. Agarwala
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Etching processes for avoiding edge stress in semiconductor chip so...
- Patent number 5,268,072
- Issue date Dec 7, 1993
- International Business Machines Corporation
- Birendra N. Agarwala
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming dual height solder interconnections
- Patent number 5,251,806
- Issue date Oct 12, 1993
- International Business Machines Corporation
- Birendra N. Agarwala
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Solder mass having conductive encapsulating arrangement
- Patent number 5,130,779
- Issue date Jul 14, 1992
- International Business Machines Corporation
- Birendra N. Agarwala
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multilayered metallurgical structure for an electronic component
- Patent number 4,985,310
- Issue date Jan 15, 1991
- International Business Machines Corp.
- Birendra N. Agarwala
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Use of tapered head pin design to improve the stress distribution i...
- Patent number 4,970,570
- Issue date Nov 13, 1990
- International Business Machines Corporation
- Birendra N. Agarwala
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Method of Forming Metal Interconnect Structures in Ultra Low-K Diel...
- Publication number 20110117737
- Publication date May 19, 2011
- Birendra Agarwala
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE AND METHOD OF FORMING METAL INTERCONNECT STRUCTURES IN UL...
- Publication number 20100176513
- Publication date Jul 15, 2010
- International Business Machines Corporation
- Birendra Agarwala
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Structure for modeling stress-induced degradation of conductive int...
- Publication number 20080231312
- Publication date Sep 25, 2008
- Kaushik Chanda
- G01 - MEASURING TESTING
Information Patent Application
Method for monitoring stress-induced degradation of conductive inte...
- Publication number 20080107149
- Publication date May 8, 2008
- Kaushik Chanda
- G01 - MEASURING TESTING
Information Patent Application
DEVICE HAVING A REDUNDANT STRUCTURE
- Publication number 20070205515
- Publication date Sep 6, 2007
- International Business Machines Corporation
- Birendra N. Agarwala
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE AND METHOD FOR MONITORING STRESS-INDUCED DEGRADATION OF C...
- Publication number 20070115018
- Publication date May 24, 2007
- International Business Machines Corporation
- Kaushik Chanda
- G01 - MEASURING TESTING
Information Patent Application
PROCESS FOR FORMING A REDUNDANT STRUCTURE
- Publication number 20070111497
- Publication date May 17, 2007
- International Business Machines Corporation
- Birendra N. Agarwala
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL DAMASCENE MULTI-LEVEL METALLIZATION
- Publication number 20070111510
- Publication date May 17, 2007
- Birendra N. Agarwala
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RELIABILITY AND FUNCTIONALITY IMPROVEMENTS ON COPPER INTERCONNECTS...
- Publication number 20060180930
- Publication date Aug 17, 2006
- International Business Machines Corporation
- Du B. Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Stacked via-stud with improved reliability in copper metallurgy
- Publication number 20060014376
- Publication date Jan 19, 2006
- International Business Machines Corporation
- Birendra N. Agarwala
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE AND METHOD FOR ELIMINATING TIME DEPENDENT DIELECTRIC BREA...
- Publication number 20040256729
- Publication date Dec 23, 2004
- International Business Machines Corporation
- Birendra N. Agarwala
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Stacked via-stud with improved reliability in copper metallurgy
- Publication number 20040101663
- Publication date May 27, 2004
- Birendra N. Agarwala
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Edge seal for a semiconductor device
- Publication number 20040087078
- Publication date May 6, 2004
- Birendra N. Agarwala
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Edge seal for a semiconductor device
- Publication number 20030157794
- Publication date Aug 21, 2003
- International Business Machines Corporation
- Birendra N. Agarwala
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integration scheme for advanced BEOL metallization including low-k...
- Publication number 20030134495
- Publication date Jul 17, 2003
- International Business Machines Corporation
- Stephen Gates
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Chip to wiring interface with single metal alloy layer applied to s...
- Publication number 20030001275
- Publication date Jan 2, 2003
- Carlos Juan Sambucetti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual damascene multi-level metallization
- Publication number 20020182855
- Publication date Dec 5, 2002
- Birendra N. Agarwala
- H01 - BASIC ELECTRIC ELEMENTS

Birendra Nath Agarwala

Person

Patents Grantslast 30 patents

Method of forming metal interconnect structures in ultra low-k diel...

Structure for modeling stress-induced degradation of conductive int...

Structure for monitoring stress-induced degradation of conductive i...

Dual damascene multi-level metallization

Structure and method for monitoring stress-induced degradation of c...

Process for forming a redundant structure

Dual-damascene metallization interconnection

Edge seal for a semiconductor device

Via barrier layers continuous with metal line barrier layers at not...

Stacked via-stud with improved reliability in copper metallurgy

Structure and method for eliminating time dependent dielectric brea...

Method of making an edge seal for a semiconductor device

Wire interconnect structure for electrically and mechanically conne...

Ball limiting metalization process for interconnection

Method for providing electrically fusible links in copper interconn...

Process of making pad structure for solder ball limiting metallurgy...

Etching processes for avoiding edge stress in semiconductor chip so...

Method of forming dual height solder interconnections

Solder mass having conductive encapsulating arrangement

Multilayered metallurgical structure for an electronic component

Use of tapered head pin design to improve the stress distribution i...

Patents Applicationslast 30 patents

Method of Forming Metal Interconnect Structures in Ultra Low-K Diel...

STRUCTURE AND METHOD OF FORMING METAL INTERCONNECT STRUCTURES IN UL...

Structure for modeling stress-induced degradation of conductive int...

Method for monitoring stress-induced degradation of conductive inte...

DEVICE HAVING A REDUNDANT STRUCTURE

STRUCTURE AND METHOD FOR MONITORING STRESS-INDUCED DEGRADATION OF C...

PROCESS FOR FORMING A REDUNDANT STRUCTURE

DUAL DAMASCENE MULTI-LEVEL METALLIZATION

RELIABILITY AND FUNCTIONALITY IMPROVEMENTS ON COPPER INTERCONNECTS...

Stacked via-stud with improved reliability in copper metallurgy

STRUCTURE AND METHOD FOR ELIMINATING TIME DEPENDENT DIELECTRIC BREA...

Stacked via-stud with improved reliability in copper metallurgy

Edge seal for a semiconductor device

Edge seal for a semiconductor device

Integration scheme for advanced BEOL metallization including low-k...

Chip to wiring interface with single metal alloy layer applied to s...

Dual damascene multi-level metallization