BLAISE FANNING

Person

Folsom, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Techniques to configure a solid state drive to operate in a storage...
- Patent number 11,042,297
- Issue date Jun 22, 2021
- Intel Corporation
- Blaise Fanning
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-level memory with direct access
- Patent number 10,817,201
- Issue date Oct 27, 2020
- Intel Corporation
- Blaise Fanning
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for shared least recently used (LRU) policy be...
- Patent number 10,657,070
- Issue date May 19, 2020
- Intel Corporation
- Daniel Greenspan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory latency management
- Patent number 10,572,339
- Issue date Feb 25, 2020
- Intel Corporation
- Robert J. Royer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive configuration of non-volatile memory
- Patent number 10,504,591
- Issue date Dec 10, 2019
- Intel Corporation
- Shekoufeh Qawami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques to configure a solid state drive to operate in a storage...
- Patent number 10,296,217
- Issue date May 21, 2019
- Intel Corporation
- Blaise Fanning
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-level memory with direct access
- Patent number 10,241,710
- Issue date Mar 26, 2019
- Intel Corporation
- Blaise Fanning
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for pinning memory pages in a multi-level syst...
- Patent number 10,185,501
- Issue date Jan 22, 2019
- Intel Corporation
- Aravindh V. Anantaraman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sending packets with expanded headers
- Patent number 10,164,880
- Issue date Dec 25, 2018
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for shared least recently used (LRU) policy be...
- Patent number 10,055,360
- Issue date Aug 21, 2018
- Intel Corporation
- Daniel Greenspan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Replacement of a block with a compressed block to increase capacity...
- Patent number 10,048,868
- Issue date Aug 14, 2018
- Intel Corporation
- Alaa R. Alameldeen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive configuration of non-volatile memory
- Patent number 10,026,475
- Issue date Jul 17, 2018
- Intel Corporation
- Shekoufeh Qawami
- G11 - INFORMATION STORAGE
Information Patent Grant
System for configuring partitions within non-volatile random access...
- Patent number 10,001,953
- Issue date Jun 19, 2018
- Intel Corporation
- Leena K. Puthiyedath
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selevtive application of interleave based on type of data to be sto...
- Patent number 9,971,691
- Issue date May 15, 2018
- Intel Corporation
- Daniel Greenspan
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for providing instant responses to sleep state tr...
- Patent number 9,958,926
- Issue date May 1, 2018
- Intel Corporation
- Leena K. Puthiyedath
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-volatile memory interface
- Patent number 9,910,771
- Issue date Mar 6, 2018
- Intel Corporation
- Eng Hun Ooi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory latency management
- Patent number 9,904,592
- Issue date Feb 27, 2018
- Intel Corporation
- Robert J. Royer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
General input/output architecture, protocol and related methods to...
- Patent number 9,860,173
- Issue date Jan 2, 2018
- Intel Corporation
- Jasmin Ajanovic
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
RAM disk using non-volatile random access memory
- Patent number 9,852,069
- Issue date Dec 26, 2017
- Intel Corporation
- James B. Crossland
- G11 - INFORMATION STORAGE
Information Patent Grant
General input/output architecture, protocol and related methods to...
- Patent number 9,836,424
- Issue date Dec 5, 2017
- Intel Corporation
- Jasmin Ajanovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and an apparatus with a sideband interface interconnecting...
- Patent number 9,753,875
- Issue date Sep 5, 2017
- Intel Corporation
- Sridhar Lakshmanamurthy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Hybrid exclusive multi-level memory architecture with memory manage...
- Patent number 9,734,079
- Issue date Aug 15, 2017
- Intel Corporation
- Dannie G. Feekes
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
General input/output architecture, protocol and related methods to...
- Patent number 9,736,071
- Issue date Aug 15, 2017
- Intel Corporation
- Jasmin Ajanovic
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multi-level memory with direct access
- Patent number 9,703,502
- Issue date Jul 11, 2017
- Intel Corporation
- Blaise Fanning
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques to configure a solid state drive to operate in a storage...
- Patent number 9,678,666
- Issue date Jun 13, 2017
- Intel Corporation
- Blaise Fanning
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Providing multiple decode options for a system-on-chip (SoC) fabric
- Patent number 9,658,978
- Issue date May 23, 2017
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for managing register information in a process...
- Patent number 9,652,259
- Issue date May 16, 2017
- Intel Corporation
- Blaise Fanning
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
General input/output architecture, protocol and related methods to...
- Patent number 9,602,408
- Issue date Mar 21, 2017
- Intel Corporation
- Jasmin Ajanovic
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
General input/output architecture, protocol and related methods to...
- Patent number 9,565,106
- Issue date Feb 7, 2017
- Intel Corporation
- Jasmin Ajanovic
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method, apparatus, system for representing, specifying and using de...
- Patent number 9,563,579
- Issue date Feb 7, 2017
- Intel Corporation
- Daniel F. Cutter
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
TECHNIQUES TO CONFIGURE A SOLID STATE DRIVE TO OPERATE IN A STORAGE...
- Publication number 20190339869
- Publication date Nov 7, 2019
- Intel Corporation
- Blaise FANNING
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-LEVEL MEMORY WITH DIRECT ACCESS
- Publication number 20190286356
- Publication date Sep 19, 2019
- Intel Corporation
- Blaise Fanning
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY LATENCY MANAGEMENT
- Publication number 20190129792
- Publication date May 2, 2019
- Intel Corporation
- Robert J. Royer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR SHARED LEAST RECENTLY USED (LRU) POLICY BE...
- Publication number 20190108138
- Publication date Apr 11, 2019
- Intel Corporation
- Daniel GREENSPAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE CONFIGURATION OF NON-VOLATILE MEMORY
- Publication number 20190057737
- Publication date Feb 21, 2019
- Intel Corporation
- Shekoufeh QAWAMI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELECTIVE DATA COMPRESSION/DECOMPRESSION FOR INTERMEMORY TRANSFER I...
- Publication number 20180095674
- Publication date Apr 5, 2018
- Intel Corporation
- Alaa R. ALAMELDEEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USING COMPRESSION TO INCREASE CAPACITY OF A MEMORY-SIDE CACHE WITH...
- Publication number 20180088822
- Publication date Mar 29, 2018
- Intel Corporation
- Alaa R. Alameldeen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELECTIVE APPLICATION OF INTERLEAVE BASED ON TYPE OF DATA TO BE STO...
- Publication number 20180074961
- Publication date Mar 15, 2018
- Intel Corporation
- Daniel Greenspan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techniques to Configure a Solid State Drive to Operate in a Storage...
- Publication number 20170336978
- Publication date Nov 23, 2017
- Intel Corporation
- Blaise FANNING
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-LEVEL MEMORY WITH DIRECT ACCESS
- Publication number 20170337009
- Publication date Nov 23, 2017
- Intel Corporation
- Blaise Fanning
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NON-VOLATILE MEMORY INTERFACE
- Publication number 20170212832
- Publication date Jul 27, 2017
- Intel Corporation
- Eng Hun Ooi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR SHARED LEAST RECENTLY USED (LRU) POLICY BE...
- Publication number 20170177502
- Publication date Jun 22, 2017
- Intel Corporation
- DANIEL GREENSPAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTILEVEL MAIN MEMORY INDIRECTION
- Publication number 20170160987
- Publication date Jun 8, 2017
- Intel Corporation
- Robert J. Royer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RAM DISK USING NON-VOLATILE RANDOM ACCESS MEMORY
- Publication number 20170139827
- Publication date May 18, 2017
- Intel Corporation
- James B. Crossland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NON-VOLATILE RANDOM ACCESS MEMORY (NVRAM) AS A REPLACEMENT FOR TRAD...
- Publication number 20170139649
- Publication date May 18, 2017
- Leena K. PUTHIYEDATH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR PINNING MEMORY PAGES IN A MULTI-LEVEL SYST...
- Publication number 20170090780
- Publication date Mar 30, 2017
- ARAVINDH V. ANANTARAMAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-LEVEL MEMORY WITH DIRECT ACCESS
- Publication number 20170075616
- Publication date Mar 16, 2017
- Intel Corporation
- Blaise Fanning
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE CONFIGURATION OF NON-VOLATILE MEMORY
- Publication number 20160203864
- Publication date Jul 14, 2016
- Intel Corporation
- SHEKOUFEH QAWAMI
- G11 - INFORMATION STORAGE
Information Patent Application
Apparatus and Method to Dynamically Expand Associativity of A Cache...
- Publication number 20160179666
- Publication date Jun 23, 2016
- Intel Corporation
- Daniel Greenspan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AGGREGATING COMPLETION MESSAGES IN A SIDEBAND INTERFACE
- Publication number 20160132447
- Publication date May 12, 2016
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-LEVEL MEMORY WITH DIRECT ACCESS
- Publication number 20160110106
- Publication date Apr 21, 2016
- Intel Corporation
- Blaise Fanning
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY LATENCY MANAGEMENT
- Publication number 20160034345
- Publication date Feb 4, 2016
- Intel Corporation
- Robert J. Royer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techniques to Configure a Solid State Drive to Operate in a Storage...
- Publication number 20160034196
- Publication date Feb 4, 2016
- Intel Corporation
- Blaise FANNING
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GENERAL INPUT/OUTPUT ARCHITECTURE, PROTOCOL AND RELATED METHODS TO...
- Publication number 20150178241
- Publication date Jun 25, 2015
- Intel Corporation
- Jasmin Ajanovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMIZED WRITE ALLOCATION FOR TWO-LEVEL MEMORY
- Publication number 20150178203
- Publication date Jun 25, 2015
- Marc Torrant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ISOCHRONOUS AGENT DATA PINNING IN A MULTI-LEVEL MEMORY SYSTEM
- Publication number 20150169439
- Publication date Jun 18, 2015
- Marc Torrant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Issuing Requests To A Fabric
- Publication number 20150113189
- Publication date Apr 23, 2015
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SENDING PACKETS WITH EXPANDED HEADERS
- Publication number 20150092779
- Publication date Apr 2, 2015
- Intel Corporation
- Sridhar Lakshmanamurthy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Providing Error Handling Support To Legacy Devices
- Publication number 20150067412
- Publication date Mar 5, 2015
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NON-VOLATILE MEMORY INTERFACE
- Publication number 20150032941
- Publication date Jan 29, 2015
- Eng Hun Ooi
- G06 - COMPUTING CALCULATING COUNTING

BLAISE FANNING

Person

Patents Grantslast 30 patents

Techniques to configure a solid state drive to operate in a storage...

Multi-level memory with direct access

Apparatus and method for shared least recently used (LRU) policy be...

Memory latency management

Adaptive configuration of non-volatile memory

Techniques to configure a solid state drive to operate in a storage...

Multi-level memory with direct access

Method and apparatus for pinning memory pages in a multi-level syst...

Sending packets with expanded headers

Apparatus and method for shared least recently used (LRU) policy be...

Replacement of a block with a compressed block to increase capacity...

Adaptive configuration of non-volatile memory

System for configuring partitions within non-volatile random access...

Selevtive application of interleave based on type of data to be sto...

Method and system for providing instant responses to sleep state tr...

Non-volatile memory interface

Memory latency management

General input/output architecture, protocol and related methods to...

RAM disk using non-volatile random access memory

General input/output architecture, protocol and related methods to...

Systems and an apparatus with a sideband interface interconnecting...

Hybrid exclusive multi-level memory architecture with memory manage...

General input/output architecture, protocol and related methods to...

Multi-level memory with direct access

Techniques to configure a solid state drive to operate in a storage...

Providing multiple decode options for a system-on-chip (SoC) fabric

Apparatus and method for managing register information in a process...

General input/output architecture, protocol and related methods to...

General input/output architecture, protocol and related methods to...

Method, apparatus, system for representing, specifying and using de...

Patents Applicationslast 30 patents

TECHNIQUES TO CONFIGURE A SOLID STATE DRIVE TO OPERATE IN A STORAGE...

MULTI-LEVEL MEMORY WITH DIRECT ACCESS

MEMORY LATENCY MANAGEMENT

APPARATUS AND METHOD FOR SHARED LEAST RECENTLY USED (LRU) POLICY BE...

ADAPTIVE CONFIGURATION OF NON-VOLATILE MEMORY

SELECTIVE DATA COMPRESSION/DECOMPRESSION FOR INTERMEMORY TRANSFER I...

USING COMPRESSION TO INCREASE CAPACITY OF A MEMORY-SIDE CACHE WITH...

SELECTIVE APPLICATION OF INTERLEAVE BASED ON TYPE OF DATA TO BE STO...

Techniques to Configure a Solid State Drive to Operate in a Storage...

MULTI-LEVEL MEMORY WITH DIRECT ACCESS

NON-VOLATILE MEMORY INTERFACE

APPARATUS AND METHOD FOR SHARED LEAST RECENTLY USED (LRU) POLICY BE...

MULTILEVEL MAIN MEMORY INDIRECTION

RAM DISK USING NON-VOLATILE RANDOM ACCESS MEMORY

NON-VOLATILE RANDOM ACCESS MEMORY (NVRAM) AS A REPLACEMENT FOR TRAD...

METHOD AND APPARATUS FOR PINNING MEMORY PAGES IN A MULTI-LEVEL SYST...

MULTI-LEVEL MEMORY WITH DIRECT ACCESS

ADAPTIVE CONFIGURATION OF NON-VOLATILE MEMORY

Apparatus and Method to Dynamically Expand Associativity of A Cache...

AGGREGATING COMPLETION MESSAGES IN A SIDEBAND INTERFACE

MULTI-LEVEL MEMORY WITH DIRECT ACCESS

MEMORY LATENCY MANAGEMENT

Techniques to Configure a Solid State Drive to Operate in a Storage...

GENERAL INPUT/OUTPUT ARCHITECTURE, PROTOCOL AND RELATED METHODS TO...

OPTIMIZED WRITE ALLOCATION FOR TWO-LEVEL MEMORY

ISOCHRONOUS AGENT DATA PINNING IN A MULTI-LEVEL MEMORY SYSTEM

Issuing Requests To A Fabric

SENDING PACKETS WITH EXPANDED HEADERS

Providing Error Handling Support To Legacy Devices

NON-VOLATILE MEMORY INTERFACE