Bob Leibowitz

Person

Boise, ID, US

People

Patents Grantslast 30 patents

Information Patent Grant
Chained bus memory device
- Patent number 10,664,411
- Issue date May 26, 2020
- Micron Technology, Inc.
- Victor Tsai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Packet deconstruction/reconstruction and link-control
- Patent number 9,929,967
- Issue date Mar 27, 2018
- Micron Technology, Inc.
- William H. Radke
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Methods for controlling host memory access with memory devices and...
- Patent number 9,811,258
- Issue date Nov 7, 2017
- Micron Technology, Inc.
- Neal A. Galbo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Chained bus method
- Patent number 9,606,885
- Issue date Mar 28, 2017
- Micron Technology, Inc.
- Victor Tsai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Host controller
- Patent number 9,588,697
- Issue date Mar 7, 2017
- Micron Technology, Inc.
- Peter Feeley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Object oriented memory in solid state devices
- Patent number 9,110,832
- Issue date Aug 18, 2015
- Micron Technology, Inc.
- Peter Feeley
- G11 - INFORMATION STORAGE
Information Patent Grant
Host controller
- Patent number 9,043,506
- Issue date May 26, 2015
- Micron Technology, Inc.
- Peter Feeley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Booting in systems having devices coupled in a chained configuration
- Patent number 9,037,842
- Issue date May 19, 2015
- Micron Technology, Inc.
- William H. Radke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for controlling host memory access with memory devices and...
- Patent number 8,918,600
- Issue date Dec 23, 2014
- Micron Technology, Inc.
- Neal A. Galbo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Object oriented memory in solid state devices
- Patent number 8,751,860
- Issue date Jun 10, 2014
- Micron Technology, Inc.
- Peter Feeley
- G11 - INFORMATION STORAGE
Information Patent Grant
Packet deconstruction/reconstruction and link-control
- Patent number 8,630,182
- Issue date Jan 14, 2014
- Micron Technology, Inc.
- William H. Radke
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Host controller
- Patent number 8,578,070
- Issue date Nov 5, 2013
- Micron Technology
- Peter Feeley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Chained bus method and device
- Patent number 8,560,735
- Issue date Oct 15, 2013
- Micron Technology, Inc.
- Victor Tsai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Booting in systems having devices coupled in a chained configuration
- Patent number 8,543,802
- Issue date Sep 24, 2013
- Micron Technology, Inc.
- William H. Radke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system controller to manage wear leveling across a plurality...
- Patent number 8,412,880
- Issue date Apr 2, 2013
- Micron Technology, Inc.
- Robert N. Leibowitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device to device flow control within a chain of devices
- Patent number 8,402,178
- Issue date Mar 19, 2013
- Micron Technology, Inc.
- Victor Y. Tsai
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Memory module with configurable input/output ports
- Patent number 8,364,856
- Issue date Jan 29, 2013
- Micron Technology, Inc.
- Terry R. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Host controller
- Patent number 8,327,040
- Issue date Dec 4, 2012
- Micron Technology, Inc.
- Peter Feeley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Booting in systems having devices coupled in a chained configuration
- Patent number 8,245,024
- Issue date Aug 14, 2012
- Micron Technology, Inc.
- William H. Radke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Packet deconstruction/reconstruction and link-control
- Patent number 8,238,244
- Issue date Aug 7, 2012
- Micron Technology, Inc.
- William H. Radke
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Methods for controlling host memory access with memory devices and...
- Patent number 8,225,052
- Issue date Jul 17, 2012
- Micron Technology, Inc.
- Neal A. Galbo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device to device flow control within a chain of devices
- Patent number 8,209,447
- Issue date Jun 26, 2012
- Micron Technology, Inc.
- Victor Y. Tsai
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Memory module with configurable input/output ports
- Patent number 8,171,181
- Issue date May 1, 2012
- Micron Technology, Inc.
- Terry R. Lee
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
CHAINED BUS METHOD
- Publication number 20170199828
- Publication date Jul 13, 2017
- Micron Technology, Inc.
- Victor Tsai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HOST CONTROLLER
- Publication number 20160004436
- Publication date Jan 7, 2016
- Micron Technology, Inc.
- Peter Feeley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS FOR CONTROLLING HOST MEMORY ACCESS WITH MEMORY DEVICES AND...
- Publication number 20150153956
- Publication date Jun 4, 2015
- Micron Technology, Inc.
- Neal A. Galbo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OBJECT ORIENTED MEMORY IN SOLID STATE DEVICES
- Publication number 20140281811
- Publication date Sep 18, 2014
- Micron Technology, Inc.
- Peter Feeley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PACKET DECONSTRUCTION/RECONSTRUCTION AND LINK-CONTROL
- Publication number 20140185620
- Publication date Jul 3, 2014
- Micron Technology, Inc.
- William H. Radke
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
HOST CONTROLLER
- Publication number 20140108678
- Publication date Apr 17, 2014
- Micron Technology, Inc.
- Peter Feeley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CHAINED BUS METHOD AND DEVICE
- Publication number 20140040507
- Publication date Feb 6, 2014
- Micron Technology, Inc.
- Victor Tsai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BOOTING IN SYSTEMS HAVING DEVICES COUPLED IN A CHAINED CONFIGURATION
- Publication number 20140025943
- Publication date Jan 23, 2014
- Micron Technology, Inc.
- William H. Radke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HOST CONTROLLER
- Publication number 20130013822
- Publication date Jan 10, 2013
- Micron Technology, Inc.
- Peter Feeley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BOOTING IN SYSTEMS HAVING DEVICES COUPLED IN A CHAINED CONFIGURATION
- Publication number 20120290826
- Publication date Nov 15, 2012
- Micron Technology, Inc.
- William H. Radke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PACKET DECONSTRUCTION/RECONSTRUCTION AND LINK-CONTROL
- Publication number 20120281537
- Publication date Nov 8, 2012
- Micron Technology, Inc.
- William H. Radke
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHODS FOR CONTROLLING HOST MEMORY ACCESS WITH MEMORY DEVICES AND...
- Publication number 20120284466
- Publication date Nov 8, 2012
- Micron Technology, Inc.
- Neal A. Galbo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICE TO DEVICE FLOW CONTROL
- Publication number 20120210025
- Publication date Aug 16, 2012
- Micron Technology, Inc.
- Victor Y. Tsai
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
MEMORY MODULE WITH CONFIGURABLE INPUT/OUTPUT PORTS
- Publication number 20120198201
- Publication date Aug 2, 2012
- Micron Technology, Inc.
- Terry R. LEE
- G11 - INFORMATION STORAGE
Information Patent Application
DEVICE TO DEVICE FLOW CONTROL
- Publication number 20110055436
- Publication date Mar 3, 2011
- Micron Technology, Inc.
- Victor Y. Tsai
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
BOOTING IN SYSTEMS HAVING DEVICES COUPLED IN A CHAINED CONFIGURATION
- Publication number 20110047366
- Publication date Feb 24, 2011
- Micron Technology, Inc.
- William H. Radke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PACKET DECONSTRUCTION/RECONSTRUCTION AND LINK-CONTROL
- Publication number 20110032823
- Publication date Feb 10, 2011
- Micron Technology, Inc.
- William H. Radke
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
OBJECT ORIENTED MEMORY IN SOLID STATE DEVICES
- Publication number 20100313065
- Publication date Dec 9, 2010
- Micron Technology, Inc.
- Peter Feeley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS FOR CONTROLLING HOST MEMORY ACCESS WITH MEMORY DEVICES AND...
- Publication number 20100312973
- Publication date Dec 9, 2010
- Micron Technology, Inc.
- Neal A. Galbo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HOST CONTROLLER
- Publication number 20100191874
- Publication date Jul 29, 2010
- Micron Technology, Inc.
- Peter Feeley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEM CONTROLLER
- Publication number 20100174851
- Publication date Jul 8, 2010
- Micron Technology, Inc.
- Robert N. Leibowitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CHAINED BUS METHOD AND DEVICE
- Publication number 20100042750
- Publication date Feb 18, 2010
- Micron Technology, Inc.
- Victor Tsai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY MODULE WITH CONFIGURABLE INPUT/OUTPUT PORTS
- Publication number 20090276545
- Publication date Nov 5, 2009
- Terry R. Lee
- G11 - INFORMATION STORAGE
Information Patent Application
ADDRESS TRANSLATION BETWEEN A MEMORY CONTROLLER AND AN EXTERNAL MEM...
- Publication number 20090157949
- Publication date Jun 18, 2009
- Robert N. Leibowitz
- G06 - COMPUTING CALCULATING COUNTING

Bob Leibowitz

Person

Patents Grantslast 30 patents

Chained bus memory device

Packet deconstruction/reconstruction and link-control

Methods for controlling host memory access with memory devices and...

Chained bus method

Host controller

Object oriented memory in solid state devices

Host controller

Booting in systems having devices coupled in a chained configuration

Methods for controlling host memory access with memory devices and...

Object oriented memory in solid state devices

Packet deconstruction/reconstruction and link-control

Host controller

Chained bus method and device

Booting in systems having devices coupled in a chained configuration

Memory system controller to manage wear leveling across a plurality...

Device to device flow control within a chain of devices

Memory module with configurable input/output ports

Host controller

Booting in systems having devices coupled in a chained configuration

Packet deconstruction/reconstruction and link-control

Methods for controlling host memory access with memory devices and...

Device to device flow control within a chain of devices

Memory module with configurable input/output ports

Patents Applicationslast 30 patents

CHAINED BUS METHOD

HOST CONTROLLER

METHODS FOR CONTROLLING HOST MEMORY ACCESS WITH MEMORY DEVICES AND...

OBJECT ORIENTED MEMORY IN SOLID STATE DEVICES

PACKET DECONSTRUCTION/RECONSTRUCTION AND LINK-CONTROL

HOST CONTROLLER

CHAINED BUS METHOD AND DEVICE

BOOTING IN SYSTEMS HAVING DEVICES COUPLED IN A CHAINED CONFIGURATION

HOST CONTROLLER

BOOTING IN SYSTEMS HAVING DEVICES COUPLED IN A CHAINED CONFIGURATION

PACKET DECONSTRUCTION/RECONSTRUCTION AND LINK-CONTROL

METHODS FOR CONTROLLING HOST MEMORY ACCESS WITH MEMORY DEVICES AND...

DEVICE TO DEVICE FLOW CONTROL

MEMORY MODULE WITH CONFIGURABLE INPUT/OUTPUT PORTS

DEVICE TO DEVICE FLOW CONTROL

BOOTING IN SYSTEMS HAVING DEVICES COUPLED IN A CHAINED CONFIGURATION

PACKET DECONSTRUCTION/RECONSTRUCTION AND LINK-CONTROL

OBJECT ORIENTED MEMORY IN SOLID STATE DEVICES

METHODS FOR CONTROLLING HOST MEMORY ACCESS WITH MEMORY DEVICES AND...

HOST CONTROLLER

MEMORY SYSTEM CONTROLLER

CHAINED BUS METHOD AND DEVICE

MEMORY MODULE WITH CONFIGURABLE INPUT/OUTPUT PORTS

ADDRESS TRANSLATION BETWEEN A MEMORY CONTROLLER AND AN EXTERNAL MEM...