Boh-Yi Huang

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Attribute-point-based timing constraint formal verification
- Patent number 11,900,035
- Issue date Feb 13, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Chao-Chun Lo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit synthesis optimization for implements on integrated circuit
- Patent number 11,900,037
- Issue date Feb 13, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Chao-Chun Lo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for mapping foundational components during des...
- Patent number 11,783,104
- Issue date Oct 10, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Chih-yuan Stephen Yu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Attribute-point-based timing constraint formal verification
- Patent number 11,620,423
- Issue date Apr 4, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Chao-Chun Lo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for mapping foundational components during des...
- Patent number 11,403,448
- Issue date Aug 2, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Chih-yuan Stephen Yu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit synthesis optimization for implements on integrated circuit
- Patent number 11,347,920
- Issue date May 31, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd
- Chao-Chun Lo
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Attribute-Point-Based Timing Constraint Formal Verification
- Publication number 20240160820
- Publication date May 16, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chao-Chun Lo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuit Synthesis Optimization for Implements on Integrated Circuit
- Publication number 20240135078
- Publication date Apr 25, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chao-Chun Lo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR MAPPING FOUNDATIONAL COMPONENTS DURING DES...
- Publication number 20240037302
- Publication date Feb 1, 2024
- TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Chih-yuan Stephen YU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Attribute-Point-Based Timing Constraint Formal Verification
- Publication number 20230205958
- Publication date Jun 29, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chao-Chun Lo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR MAPPING FOUNDATIONAL COMPONENTS DURING DES...
- Publication number 20220414304
- Publication date Dec 29, 2022
- TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Chih-yuan Stephen YU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuit Synthesis Optimization for Implements on Integrated Circuit
- Publication number 20220284162
- Publication date Sep 8, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chao-Chun Lo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuit Synthesis Optimization for Implements on Integrated Circuit
- Publication number 20220121798
- Publication date Apr 21, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chao-Chun Lo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Attribute-Point-Based Timing Constraint Formal Verification
- Publication number 20220083717
- Publication date Mar 17, 2022
- Taiwan Semiconductor Manufacturing Company Limited
- Chao-Chun Lo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems and Methods for Generating Synthesizable Netlists From Regi...
- Publication number 20220012392
- Publication date Jan 13, 2022
- Taiwan Semiconductor Manufacturing Company Limited
- Boh-Yi Huang
- G06 - COMPUTING CALCULATING COUNTING

Boh-Yi Huang

Person

Patents Grantslast 30 patents

Attribute-point-based timing constraint formal verification

Circuit synthesis optimization for implements on integrated circuit

Apparatus and method for mapping foundational components during des...

Attribute-point-based timing constraint formal verification

Apparatus and method for mapping foundational components during des...

Circuit synthesis optimization for implements on integrated circuit

Patents Applicationslast 30 patents

Attribute-Point-Based Timing Constraint Formal Verification

Circuit Synthesis Optimization for Implements on Integrated Circuit

APPARATUS AND METHOD FOR MAPPING FOUNDATIONAL COMPONENTS DURING DES...

Attribute-Point-Based Timing Constraint Formal Verification

APPARATUS AND METHOD FOR MAPPING FOUNDATIONAL COMPONENTS DURING DES...

Circuit Synthesis Optimization for Implements on Integrated Circuit

Circuit Synthesis Optimization for Implements on Integrated Circuit

Attribute-Point-Based Timing Constraint Formal Verification

Systems and Methods for Generating Synthesizable Netlists From Regi...