Bohuslav Rychlik

Person

San Diego, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Providing content-aware cache replacement and insertion policies in...
- Patent number 12,182,036
- Issue date Dec 31, 2024
- QUALCOMM Incorporated
- George Patsilaras
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Allocation of data sub-tensors onto hardware sub-arrays
- Patent number 12,093,155
- Issue date Sep 17, 2024
- QUALCOMM Incorporated
- Hee Jun Park
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data write from pre-programmed register
- Patent number 11,748,252
- Issue date Sep 5, 2023
- RAMBUS INC.
- Thomas J. Sheffler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DRAM with command-differentiated storage of internally and external...
- Patent number 11,720,485
- Issue date Aug 8, 2023
- RAMBUS INC.
- Thomas J. Sheffler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Space and time cache coherency
- Patent number 11,681,624
- Issue date Jun 20, 2023
- QUALCOMM Incorporated
- Andrew Edmund Turner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data re-encoding for energy-efficient data transfer in a computing...
- Patent number 11,636,057
- Issue date Apr 25, 2023
- QUALCOMM Incorporated
- Engin Ipek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-stage biometric authentication
- Patent number 11,256,894
- Issue date Feb 22, 2022
- QUALCOMM Incorporated
- Wesley James Holland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory component that performs data write from pre-programmed register
- Patent number 11,204,863
- Issue date Dec 21, 2021
- RAMBUS INC.
- Thomas J. Sheffler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for mixed tile-aware and tile-unaware traffic thr...
- Patent number 11,016,898
- Issue date May 25, 2021
- QUALCOMM Incorporated
- Andrew Edmund Turner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for intelligent tile-based prefetching of image f...
- Patent number 10,747,671
- Issue date Aug 18, 2020
- QUALCOMM Incorporated
- Wesley James Holland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for optimized execution using resource utiliza...
- Patent number 10,592,292
- Issue date Mar 17, 2020
- QUALCOMM Incorporated
- Mehrdad Mohammad H. Reshadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single command, multiple column-operation memory device
- Patent number 10,552,310
- Issue date Feb 4, 2020
- Rambus Inc.
- Thomas J. Sheffler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache coherence with functional address apertures
- Patent number 10,503,643
- Issue date Dec 10, 2019
- QUALCOMM Incorporated
- Bohuslav Rychlik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware managed power collapse and clock wake-up for memory manage...
- Patent number 10,386,904
- Issue date Aug 20, 2019
- QUALCOMM Incorporated
- Jason Edward Podaima
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic mapping of applications on NVRAM/DRAM hybrid memory
- Patent number 10,338,837
- Issue date Jul 2, 2019
- QUALCOMM Incorporated
- Subrato Kumar De
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic cache coherency for page table data
- Patent number 10,339,058
- Issue date Jul 2, 2019
- QUALCOMM Incorporated
- Andrew Edmund Turner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache line compaction of compressed data segments
- Patent number 10,261,910
- Issue date Apr 16, 2019
- QUALCOMM Incorporated
- Andrew Edmund Turner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic input/output coherency
- Patent number 10,255,181
- Issue date Apr 9, 2019
- QUALCOMM Incorporated
- Andrew Edmund Turner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid input/output coherent write
- Patent number 10,248,565
- Issue date Apr 2, 2019
- QUALCOMM Incorporated
- Andrew Edmund Turner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transaction elimination using metadata
- Patent number 10,114,585
- Issue date Oct 30, 2018
- QUALCOMM Incorporated
- Jeffrey Hao Chu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnect distributed virtual memory (DVM) message preemptive re...
- Patent number 9,910,799
- Issue date Mar 6, 2018
- QUALCOMM Incorporated
- Christophe Avoinne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single command, multiple column-operation memory device
- Patent number 9,898,400
- Issue date Feb 20, 2018
- Rambus Inc.
- Thomas A. Sheffler
- G11 - INFORMATION STORAGE
Information Patent Grant
Power aware padding
- Patent number 9,858,196
- Issue date Jan 2, 2018
- QUALCOMM Incorporated
- George Patsilaras
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods of memory bit flip identification for debugging...
- Patent number 9,846,612
- Issue date Dec 19, 2017
- QUALCOMM Incorporated
- Madan Krishnappa
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Providing memory management unit (MMU) partitioned translation cach...
- Patent number 9,824,015
- Issue date Nov 21, 2017
- QUALCOMM Incorporated
- Jason Edward Podaima
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for optimized execution using resource utiliza...
- Patent number 9,804,893
- Issue date Oct 31, 2017
- QUALCOMM Incorporated
- Mehrdad Mohammad H. Reshadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Command-driven translation pre-fetch for memory management units
- Patent number 9,792,215
- Issue date Oct 17, 2017
- QUALCOMM Incorporated
- Jason Edward Podaima
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Providing memory management unit (MMU) partitioned translation cach...
- Patent number 9,785,559
- Issue date Oct 10, 2017
- QUALCOMM Incorporated
- Jason Edward Podaima
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Providing memory management unit (MMU) partitioned translation cach...
- Patent number 9,747,213
- Issue date Aug 29, 2017
- QUALCOMM Incorporated
- Jason Edward Podaima
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for improved memory performance using cache level...
- Patent number 9,747,209
- Issue date Aug 29, 2017
- QUALCOMM Incorporated
- Feng Wang
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PROCESSOR-BASED SYSTEM EMPLOYING A SAFETY ISLAND ARCHITECTURE FOR F...
- Publication number 20240326867
- Publication date Oct 3, 2024
- QUALCOMM Incorporated
- Sriram Hariharan
- B60 - VEHICLES IN GENERAL
Information Patent Application
PROCESSOR SYSTEM INCLUDING TABLE-BASED MEMORY PROTECTION FOR IMPROV...
- Publication number 20240273030
- Publication date Aug 15, 2024
- QUALCOMM Incorporated
- James BALL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROVIDING CONTENT-AWARE CACHE REPLACEMENT AND INSERTION POLICIES IN...
- Publication number 20240264950
- Publication date Aug 8, 2024
- QUALCOMM Incorporated
- George Patsilaras
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MATRIX MULTIPLIER IMPLEMENTED TO PERFORM CONCURRENT STORE AND MULTI...
- Publication number 20240169018
- Publication date May 23, 2024
- QUALCOMM Incorporated
- Hamza OMAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELECTIVE REFRESH FOR MEMORY DEVICES
- Publication number 20230359373
- Publication date Nov 9, 2023
- QUALCOMM Incorporated
- Engin Ipek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DRAM WITH COMMAND-DIFFERENTIATED STORAGE OF INTERNALLY AND EXTERNAL...
- Publication number 20230325309
- Publication date Oct 12, 2023
- Rambus Inc.
- Thomas J. Sheffler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ALLOCATION OF DATA SUB-TENSORS ONTO HARDWARE SUB-ARRAYS
- Publication number 20230100036
- Publication date Mar 30, 2023
- QUALCOMM Incorporated
- Hee Jun PARK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA RE-ENCODING FOR ENERGY-EFFICIENT DATA TRANSFER IN A COMPUTING...
- Publication number 20230031310
- Publication date Feb 2, 2023
- QUALCOMM Incorporated
- ENGIN IPEK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DRAM WITH COMMAND-DIFFERENTIATED STORAGE OF INTERNALLY AND EXTERNAL...
- Publication number 20220253378
- Publication date Aug 11, 2022
- Rambus Inc.
- Thomas J. Sheffler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA WRITE FROM PRE-PROGRAMMED REGISTER
- Publication number 20220206936
- Publication date Jun 30, 2022
- Rambus Inc.
- Thomas J. Sheffler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ OPTIONAL AND WRITE OPTIONAL COMMANDS
- Publication number 20220113901
- Publication date Apr 14, 2022
- QUALCOMM Incorporated
- Andrew Edmund TURNER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPACE AND TIME CACHE COHERENCY
- Publication number 20220019534
- Publication date Jan 20, 2022
- QUALCOMM Incorporated
- Andrew Edmund Turner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR MIXED TILE-AWARE AND TILE-UNAWARE TRAFFIC THR...
- Publication number 20210200679
- Publication date Jul 1, 2021
- QUALCOMM Incorporated
- Andrew Edmund Turner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-STAGE BIOMETRIC AUTHENTICATION
- Publication number 20210174047
- Publication date Jun 10, 2021
- QUALCOMM Incorporated
- Wesley James HOLLAND
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD FOR MIXED TILE-AWARE AND TILE-UNAWARE TRAFFIC THR...
- Publication number 20210049099
- Publication date Feb 18, 2021
- QUALCOMM Incorporated
- Andrew Edmund Turner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SINGLE COMMAND, MULTIPLE COLUMN-OPERATION MEMORY DEVICE
- Publication number 20200257619
- Publication date Aug 13, 2020
- RAMBUS INC.
- Thomas J. Sheffler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR INTELLIGENT TILE-BASED PREFETCHING OF IMAGE F...
- Publication number 20200250097
- Publication date Aug 6, 2020
- QUALCOMM Incorporated
- WESLEY JAMES HOLLAND
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR INTELLIGENT TILE-BASED MEMORY BANDWIDTH MANAG...
- Publication number 20200250101
- Publication date Aug 6, 2020
- QUALCOMM Incorporated
- GEORGE PATSILARAS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE MANAGED POWER COLLAPSE AND CLOCK WAKE-UP FOR MEMORY MANAGE...
- Publication number 20190324512
- Publication date Oct 24, 2019
- QUALCOMM Incorporated
- Jason Edward PODAIMA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reverse Tiling
- Publication number 20190012204
- Publication date Jan 10, 2019
- QUALCOMM Incorporated
- Andrew TURNER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Automatic Cache Coherency For Page Table Data
- Publication number 20180336133
- Publication date Nov 22, 2018
- QUALCOMM Incorporated
- Andrew Edmund TURNER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Input/output-coherent Look-ahead Cache Access
- Publication number 20180336136
- Publication date Nov 22, 2018
- QUALCOMM Incorporated
- Farrukh HIJAZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SINGLE COMMAND, MULTIPLE COLUMN-OPERATION MEMORY DEVICE
- Publication number 20180267891
- Publication date Sep 20, 2018
- RAMBUS INC.
- Thomas A. Sheffler
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
TRANSACTION ELIMINATION USING METADATA
- Publication number 20180253258
- Publication date Sep 6, 2018
- QUALCOMM Incorporated
- Jeffrey Hao CHU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamic Input/Output Coherency
- Publication number 20180081804
- Publication date Mar 22, 2018
- QUALCOMM Incorporated
- Andrew Edmund Turner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hybrid Input/Output Coherent Write
- Publication number 20180081809
- Publication date Mar 22, 2018
- QUALCOMM Incorporated
- Andrew Edmund Turner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SINGLE COMMAND, MULTIPLE COLUMN-OPERATION MEMORY DEVICE
- Publication number 20170293552
- Publication date Oct 12, 2017
- RAMBUS INC.
- Thomas A. Sheffler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE MANAGED POWER COLLAPSE AND CLOCK WAKE-UP FOR MEMORY MANAGE...
- Publication number 20170285705
- Publication date Oct 5, 2017
- QUALCOMM Incorporated
- Jason Edward PODAIMA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Interconnect Distributed Virtual Memory Message Preemptive Responding
- Publication number 20170286335
- Publication date Oct 5, 2017
- QUALCOMM Incorporated
- Christophe Avoinne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR OPTIMIZED EXECUTION USING RESOURCE UTILIZA...
- Publication number 20170255497
- Publication date Sep 7, 2017
- QUALCOMM Incorporated
- Mehrdad Mohammad H. RESHADI
- G06 - COMPUTING CALCULATING COUNTING

Bohuslav Rychlik

Person

Patents Grantslast 30 patents

Providing content-aware cache replacement and insertion policies in...

Allocation of data sub-tensors onto hardware sub-arrays

Data write from pre-programmed register

DRAM with command-differentiated storage of internally and external...

Space and time cache coherency

Data re-encoding for energy-efficient data transfer in a computing...

Multi-stage biometric authentication

Memory component that performs data write from pre-programmed register

System and method for mixed tile-aware and tile-unaware traffic thr...

System and method for intelligent tile-based prefetching of image f...

Method and apparatus for optimized execution using resource utiliza...

Single command, multiple column-operation memory device

Cache coherence with functional address apertures

Hardware managed power collapse and clock wake-up for memory manage...

Dynamic mapping of applications on NVRAM/DRAM hybrid memory

Automatic cache coherency for page table data

Cache line compaction of compressed data segments

Dynamic input/output coherency

Hybrid input/output coherent write

Transaction elimination using metadata

Interconnect distributed virtual memory (DVM) message preemptive re...

Single command, multiple column-operation memory device

Power aware padding

Systems and methods of memory bit flip identification for debugging...

Providing memory management unit (MMU) partitioned translation cach...

Method and apparatus for optimized execution using resource utiliza...

Command-driven translation pre-fetch for memory management units

Providing memory management unit (MMU) partitioned translation cach...

Providing memory management unit (MMU) partitioned translation cach...

System and method for improved memory performance using cache level...

Patents Applicationslast 30 patents

PROCESSOR-BASED SYSTEM EMPLOYING A SAFETY ISLAND ARCHITECTURE FOR F...

PROCESSOR SYSTEM INCLUDING TABLE-BASED MEMORY PROTECTION FOR IMPROV...

PROVIDING CONTENT-AWARE CACHE REPLACEMENT AND INSERTION POLICIES IN...

MATRIX MULTIPLIER IMPLEMENTED TO PERFORM CONCURRENT STORE AND MULTI...

SELECTIVE REFRESH FOR MEMORY DEVICES

DRAM WITH COMMAND-DIFFERENTIATED STORAGE OF INTERNALLY AND EXTERNAL...

ALLOCATION OF DATA SUB-TENSORS ONTO HARDWARE SUB-ARRAYS

DATA RE-ENCODING FOR ENERGY-EFFICIENT DATA TRANSFER IN A COMPUTING...

DRAM WITH COMMAND-DIFFERENTIATED STORAGE OF INTERNALLY AND EXTERNAL...

DATA WRITE FROM PRE-PROGRAMMED REGISTER

READ OPTIONAL AND WRITE OPTIONAL COMMANDS

SPACE AND TIME CACHE COHERENCY

SYSTEM AND METHOD FOR MIXED TILE-AWARE AND TILE-UNAWARE TRAFFIC THR...

MULTI-STAGE BIOMETRIC AUTHENTICATION

SYSTEM AND METHOD FOR MIXED TILE-AWARE AND TILE-UNAWARE TRAFFIC THR...

SINGLE COMMAND, MULTIPLE COLUMN-OPERATION MEMORY DEVICE

SYSTEM AND METHOD FOR INTELLIGENT TILE-BASED PREFETCHING OF IMAGE F...

SYSTEM AND METHOD FOR INTELLIGENT TILE-BASED MEMORY BANDWIDTH MANAG...

HARDWARE MANAGED POWER COLLAPSE AND CLOCK WAKE-UP FOR MEMORY MANAGE...

Reverse Tiling

Automatic Cache Coherency For Page Table Data

Input/output-coherent Look-ahead Cache Access

SINGLE COMMAND, MULTIPLE COLUMN-OPERATION MEMORY DEVICE

TRANSACTION ELIMINATION USING METADATA

Dynamic Input/Output Coherency

Hybrid Input/Output Coherent Write

SINGLE COMMAND, MULTIPLE COLUMN-OPERATION MEMORY DEVICE

HARDWARE MANAGED POWER COLLAPSE AND CLOCK WAKE-UP FOR MEMORY MANAGE...

Interconnect Distributed Virtual Memory Message Preemptive Responding

METHOD AND APPARATUS FOR OPTIMIZED EXECUTION USING RESOURCE UTILIZA...