Botaro Hirosaki

Person

Tokyo, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Digital communicationn system using partial response and bipolar co...
- Patent number 5,093,843
- Issue date Mar 3, 1992
- NEC Corporation
- Botaro Hirosaki
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Rate conversion digital filter
- Patent number 4,893,265
- Issue date Jan 9, 1990
- NEC Corporation
- Botaro Hirosaki
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Destuffing circuit with a digital phase-locked loop
- Patent number 4,803,680
- Issue date Feb 7, 1989
- NEC Corporation
- Yoshinori Rokugo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Differential coding system and apparatus therefor
- Patent number 4,661,945
- Issue date Apr 28, 1987
- NEC Corporation
- Botaro Hirosaki
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Phase-locked loop with supplemental phase signal
- Patent number 4,642,575
- Issue date Feb 10, 1987
- NEC Corporation
- Botaro Hirosaki
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Apparatus for cancelling periodic carrier phase jitters
- Patent number 4,639,939
- Issue date Jan 27, 1987
- NEC Corporation
- Botaro Hirosaki
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method of synchronizing parallel channels of orthogonally multiplex...
- Patent number 4,621,355
- Issue date Nov 4, 1986
- NEC Corporation
- Botaro Hirosaki
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Selective fading protection system
- Patent number 4,613,975
- Issue date Sep 23, 1986
- NEC Corporation
- Hidehito Aoyagi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Frequency offset correcting circuit
- Patent number 4,604,583
- Issue date Aug 5, 1986
- NEC Corporation
- Hidehito Aoyagi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Circuit for establishing accurate sample timing
- Patent number 4,575,682
- Issue date Mar 11, 1986
- NEC Corporation
- Hidehito Aoyagi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Framing circuit for digital system
- Patent number 4,541,104
- Issue date Sep 10, 1985
- NEC Corporation
- Botaro Hirosaki
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Timing recovery circuit
- Patent number 4,423,518
- Issue date Dec 27, 1983
- Nippon Electric Co., Ltd.
- Botaro Hirosaki
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Modem to be coupled to a directional transmission line of an SS mul...
- Patent number 4,392,220
- Issue date Jul 5, 1983
- Nippon Electric Co., Ltd.
- Botaro Hirosaki
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Transmitter and receiver for an othogonally multiplexed QAM signal...
- Patent number 4,300,229
- Issue date Nov 10, 1981
- Nippon Electric Co., Ltd.
- Botaro Hirosaki
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Botaro Hirosaki

Person

Patents Grantslast 30 patents

Digital communicationn system using partial response and bipolar co...

Rate conversion digital filter

Destuffing circuit with a digital phase-locked loop

Differential coding system and apparatus therefor

Phase-locked loop with supplemental phase signal

Apparatus for cancelling periodic carrier phase jitters

Method of synchronizing parallel channels of orthogonally multiplex...

Selective fading protection system

Frequency offset correcting circuit

Circuit for establishing accurate sample timing

Framing circuit for digital system

Timing recovery circuit

Modem to be coupled to a directional transmission line of an SS mul...

Transmitter and receiver for an othogonally multiplexed QAM signal...