Brad Garni

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Physically unclonable function having source bias transistors
- Patent number 11,233,663
- Issue date Jan 25, 2022
- NXP USA, INC.
- Alexander Hoefler
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Data processing system and method for generating a digital code wit...
- Patent number 11,056,161
- Issue date Jul 6, 2021
- NXP USA, INC.
- Nihaar N. Mahatme
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Physically unclonable function and method for generating a digital...
- Patent number 10,574,469
- Issue date Feb 25, 2020
- NXP USA, INC.
- Brad John Garni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory array with read only cells having multiple states and method...
- Patent number 10,453,544
- Issue date Oct 22, 2019
- NXP USA, INC.
- Jianan Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device with single-event latch-up prevention circuitry
- Patent number 9,123,545
- Issue date Sep 1, 2015
- Jianan Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SRAM with embedded ROM
- Patent number 8,995,178
- Issue date Mar 31, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Jianan Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Single event latch-up prevention techniques for a semiconductor device
- Patent number 8,685,800
- Issue date Apr 1, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Jianan Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory circuit with sense amplifier
- Patent number 7,881,138
- Issue date Feb 1, 2011
- FREESCALE SEMICONDUCTOR, INC.
- Brad Garni
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense amplifier with multiple bits sharing a common reference
- Patent number 7,292,484
- Issue date Nov 6, 2007
- FREESCALE SEMICONDUCTOR, INC.
- Thomas W. Andre
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit and method for reading a toggle memory cell
- Patent number 6,744,663
- Issue date Jun 1, 2004
- Motorola, Inc.
- Brad J. Garni
- G11 - INFORMATION STORAGE
Information Patent Grant
Balanced load memory and method of operation
- Patent number 6,711,068
- Issue date Mar 23, 2004
- Motorola, Inc.
- Chitra K. Subramanian
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit and method of writing a toggle memory
- Patent number 6,693,824
- Issue date Feb 17, 2004
- Motorola, Inc.
- Joseph J. Nahas
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
PHYSICALLY UNCLONABLE FUNCTION HAVING SOURCE BIAS TRANSISTORS
- Publication number 20220029834
- Publication date Jan 27, 2022
- NXP USA, Inc.
- Alexander Hoefler
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DATA PROCESSING SYSTEM AND METHOD FOR GENERATING A DIGITAL CODE WIT...
- Publication number 20210027814
- Publication date Jan 28, 2021
- NXP USA, Inc.
- Nihaar N. Mahatme
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
MEMORY ARRAY WITH READ ONLY CELLS HAVING MULTIPLE STATES AND METHOD...
- Publication number 20160172052
- Publication date Jun 16, 2016
- FREESCALE SEMICONDUCTOR, INC.
- JIANAN YANG
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE WITH SINGLE-EVENT LATCH-UP PREVENTION CIRCUITRY
- Publication number 20140167102
- Publication date Jun 19, 2014
- FREESCALE SEMICONDUCTOR, INC.
- JIANAN YANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SINGLE-EVENT LATCH-UP PREVENTION TECHNIQUES FOR A SEMICONDUCTOR DEVICE
- Publication number 20140027810
- Publication date Jan 30, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Jianan Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY CIRCUIT WITH SENSE AMPLIFIER
- Publication number 20090290443
- Publication date Nov 26, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Brad Garni
- G11 - INFORMATION STORAGE
Information Patent Application
BALANCED LOAD MEMORY AND METHOD OF OPERATION
- Publication number 20040001361
- Publication date Jan 1, 2004
- Chitra K. Subramanian
- G11 - INFORMATION STORAGE
Information Patent Application
CIRCUIT AND METHOD OF WRITING A TOGGLE MEMORY
- Publication number 20040001352
- Publication date Jan 1, 2004
- Joseph J. Nahas
- G11 - INFORMATION STORAGE

Person

Patents Grantslast 30 patents

Physically unclonable function having source bias transistors

Data processing system and method for generating a digital code wit...

Physically unclonable function and method for generating a digital...

Memory array with read only cells having multiple states and method...

Semiconductor device with single-event latch-up prevention circuitry

SRAM with embedded ROM

Single event latch-up prevention techniques for a semiconductor device

Memory circuit with sense amplifier

Sense amplifier with multiple bits sharing a common reference

Circuit and method for reading a toggle memory cell

Balanced load memory and method of operation

Circuit and method of writing a toggle memory

Patents Applicationslast 30 patents

PHYSICALLY UNCLONABLE FUNCTION HAVING SOURCE BIAS TRANSISTORS

DATA PROCESSING SYSTEM AND METHOD FOR GENERATING A DIGITAL CODE WIT...

MEMORY ARRAY WITH READ ONLY CELLS HAVING MULTIPLE STATES AND METHOD...

SEMICONDUCTOR DEVICE WITH SINGLE-EVENT LATCH-UP PREVENTION CIRCUITRY

SINGLE-EVENT LATCH-UP PREVENTION TECHNIQUES FOR A SEMICONDUCTOR DEVICE

MEMORY CIRCUIT WITH SENSE AMPLIFIER

BALANCED LOAD MEMORY AND METHOD OF OPERATION

CIRCUIT AND METHOD OF WRITING A TOGGLE MEMORY