Brad Sharpe-Geisler

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Input/output bus protection systems and methods for programmable lo...
- Patent number 11,206,025
- Issue date Dec 21, 2021
- Lattice Semiconductor Corporation
- Chwei-Po Chew
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple mode device implementation for programmable logic devices
- Patent number 10,630,269
- Issue date Apr 21, 2020
- Lattice Semiconductor Corporation
- Brad Sharpe-Geisler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Deterministic read back and error detection for programmable logic...
- Patent number 10,417,078
- Issue date Sep 17, 2019
- LATTICE SEMICONDUCTOR CORPORATION
- Loren McLaury
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flexible ripple mode device implementation for programmable logic d...
- Patent number 10,382,021
- Issue date Aug 13, 2019
- LATTICE SEMICONDUCTOR CORPORATION
- Brad Sharpe-Geisler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple mode device implementation for programmable logic devices
- Patent number 10,141,917
- Issue date Nov 27, 2018
- Lattice Semiconductor Corporation
- Brad Sharpe-Geisler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selective power gating of routing resource configuration memory bit...
- Patent number 10,079,054
- Issue date Sep 18, 2018
- LATTICE SEMICONDUCTOR CORPORATION
- Senani Gunaratna
- G11 - INFORMATION STORAGE
Information Patent Grant
Flexible ripple mode device implementation for programmable logic d...
- Patent number 9,735,761
- Issue date Aug 15, 2017
- Lattice Semiconductor Corporation
- Brad Sharpe-Geisler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiple mode device implementation for programmable logic devices
- Patent number 9,716,491
- Issue date Jul 25, 2017
- LATTICE SEMICONDUCTOR CORPORATION
- Brad Sharpe-Geisler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High speed complementary NMOS LUT logic
- Patent number 9,543,950
- Issue date Jan 10, 2017
- LATTICE SEMICONDUCTOR CORPORATION
- Brad Sharpe-Geisler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
ESD protection using shared RC trigger
- Patent number 9,537,308
- Issue date Jan 3, 2017
- Lattice Semiconductor Corporation
- Keith Truong
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Hot-socket circuitry
- Patent number 9,515,643
- Issue date Dec 6, 2016
- LATTICE SEMICONDUCTOR CORPORATION
- Keith Truong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
PVT compensation scheme for output buffers
- Patent number 9,287,872
- Issue date Mar 15, 2016
- LATTICESEMICONDUCTORCORPORATION
- Siak Chon Kee
- G05 - CONTROLLING REGULATING
Information Patent Grant
Shared logic for multiple registers with asynchronous initialization
- Patent number 9,252,755
- Issue date Feb 2, 2016
- LATTICE SEMICONDUCTOR CORPORATION
- Brad Sharpe-Geisler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dual-port SRAM with bit line clamping
- Patent number 8,971,146
- Issue date Mar 3, 2015
- Lattice Semiconductor Corporation
- Brad Sharpe-Geisler
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit package with input capacitance compensation
- Patent number 8,643,168
- Issue date Feb 4, 2014
- Lattice Semiconductor Corporation
- Ban P. Wong
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual-port SRAM with bit line clamping
- Patent number 8,451,679
- Issue date May 28, 2013
- Lattice Semiconductor Corporation
- Brad Sharpe-Geisler
- G11 - INFORMATION STORAGE
Information Patent Grant
Soft error upset hardened integrated circuit systems and methods
- Patent number 7,868,646
- Issue date Jan 11, 2011
- Lattice Semiconductor Corporation
- Brad Sharpe-Geisler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device with a multi-data rate SDRAM interface
- Patent number 7,787,326
- Issue date Aug 31, 2010
- Lattice Semiconductor Corporation
- Brad Sharpe-Geisler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Soft error upset hardened integrated circuit systems and methods
- Patent number 7,741,865
- Issue date Jun 22, 2010
- Lattice Semiconductor Corporation
- Brad Sharpe-Geisler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High fan-out signal routing systems and methods
- Patent number 7,576,563
- Issue date Aug 18, 2009
- Lattice Semiconductor Corporation
- Qin Wei
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device with power-saving architecture
- Patent number 7,558,143
- Issue date Jul 7, 2009
- Lattice Semiconductor Corporation
- Henry Law
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable logic devices with distributed memory
- Patent number 7,459,935
- Issue date Dec 2, 2008
- Lattice Semiconductor Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Input/output systems and methods
- Patent number 7,411,419
- Issue date Aug 12, 2008
- Lattice Semiconductor Corporation
- Kiet Truong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device with power-saving architecture
- Patent number 7,376,037
- Issue date May 20, 2008
- Lattice Semiconductor Corporation
- Henry Law
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable logic devices with distributed memory and non-volatile...
- Patent number 7,355,441
- Issue date Apr 8, 2008
- Lattice Semiconductor Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device with a double data rate SDRAM interface
- Patent number 7,342,838
- Issue date Mar 11, 2008
- Lattice Semiconductor Corporation
- Brad Sharpe-Geisler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable interconnect architecture for programmable logic devices
- Patent number 7,256,613
- Issue date Aug 14, 2007
- Lattice Semiconductor Corporation
- Brad Sharpe-Geisler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Scalable serializer-deserializer architecture and programmable inte...
- Patent number 7,098,685
- Issue date Aug 29, 2006
- Lattice Semiconductor Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Zero-power CMOS non-volatile memory cell having an avalanche inject...
- Patent number 6,028,789
- Issue date Feb 22, 2000
- Vantis Corporation
- Sunil D. Mehta
- G11 - INFORMATION STORAGE
Information Patent Grant
Low-power sense amplifier with feedback
- Patent number 5,189,322
- Issue date Feb 23, 1993
- Advanced Micro Devices, Inc.
- Melvin D. Chan
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
INPUT/OUTPUT BUS PROTECTION SYSTEMS AND METHODS FOR PROGRAMMABLE LO...
- Publication number 20210288651
- Publication date Sep 16, 2021
- Lattice Semiconductor Corporation
- Chwei-Po CHEW
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE MODE DEVICE IMPLEMENTATION FOR PROGRAMMABLE LOGIC DEVICES
- Publication number 20190158073
- Publication date May 23, 2019
- Lattice Semiconductor Corporation
- Brad Sharpe-Geisler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE MODE DEVICE IMPLEMENTATION FOR PROGRAMMABLE LOGIC DEVICES
- Publication number 20170324401
- Publication date Nov 9, 2017
- Lattice Semiconductor Corporation
- Brad Sharpe-Geisler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLEXIBLE RIPPLE MODE DEVICE IMPLEMENTATION FOR PROGRAMMABLE LOGIC D...
- Publication number 20170324400
- Publication date Nov 9, 2017
- Lattice Semiconductor Corporation
- Brad Sharpe-Geisler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DETERMINISTIC READ BACK AND ERROR DETECTION FOR PROGRAMMABLE LOGIC...
- Publication number 20170293518
- Publication date Oct 12, 2017
- Lattice Semiconductor Corporation
- Loren McLaury
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLEXIBLE RIPPLE MODE DEVICE IMPLEMENTATION FOR PROGRAMMABLE LOGIC D...
- Publication number 20160028400
- Publication date Jan 28, 2016
- Lattice Semiconductor Corporation
- Brad Sharpe-Geisler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARED LOGIC FOR MULTIPLE REGISTERS WITH ASYNCHRONOUS INITIALIZATION
- Publication number 20160028383
- Publication date Jan 28, 2016
- Lattice Semiconductor Corporation
- Brad Sharpe-Geisler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MULTIPLE MODE DEVICE IMPLEMENTATION FOR PROGRAMMABLE LOGIC DEVICES
- Publication number 20160028401
- Publication date Jan 28, 2016
- Lattice Semiconductor Corporation
- Brad Sharpe-Geisler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH SPEED COMPLEMENTARY NMOS LUT LOGIC
- Publication number 20160020767
- Publication date Jan 21, 2016
- Lattice Semiconductor Corporation
- Brad Sharpe-Geisler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PVT Compensation Scheme for Output Buffers
- Publication number 20150372679
- Publication date Dec 24, 2015
- Lattice Semiconductor Corporation
- Siak Chon Kee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Hot-Socket Circuitry
- Publication number 20150194953
- Publication date Jul 9, 2015
- Lattice Semiconductor Corporation
- Keith Truong
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
ESD PROTECTION USING SHARED RC TRIGGER
- Publication number 20150155707
- Publication date Jun 4, 2015
- Lattice Semiconductor Corporation
- Keith Truong
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
DUAL-PORT SRAM WITH BIT LINE CLAMPING
- Publication number 20130258761
- Publication date Oct 3, 2013
- Lattice Semiconductor Corporation
- Brad Sharpe-Geisler
- G11 - INFORMATION STORAGE

Brad Sharpe-Geisler

Person

Patents Grantslast 30 patents

Input/output bus protection systems and methods for programmable lo...

Multiple mode device implementation for programmable logic devices

Deterministic read back and error detection for programmable logic...

Flexible ripple mode device implementation for programmable logic d...

Multiple mode device implementation for programmable logic devices

Selective power gating of routing resource configuration memory bit...

Flexible ripple mode device implementation for programmable logic d...

Multiple mode device implementation for programmable logic devices

High speed complementary NMOS LUT logic

ESD protection using shared RC trigger

Hot-socket circuitry

PVT compensation scheme for output buffers

Shared logic for multiple registers with asynchronous initialization

Dual-port SRAM with bit line clamping

Integrated circuit package with input capacitance compensation

Dual-port SRAM with bit line clamping

Soft error upset hardened integrated circuit systems and methods

Programmable logic device with a multi-data rate SDRAM interface

Soft error upset hardened integrated circuit systems and methods

High fan-out signal routing systems and methods

Programmable logic device with power-saving architecture

Programmable logic devices with distributed memory

Input/output systems and methods

Programmable logic device with power-saving architecture

Programmable logic devices with distributed memory and non-volatile...

Programmable logic device with a double data rate SDRAM interface

Programmable interconnect architecture for programmable logic devices

Scalable serializer-deserializer architecture and programmable inte...

Zero-power CMOS non-volatile memory cell having an avalanche inject...

Low-power sense amplifier with feedback

Patents Applicationslast 30 patents

INPUT/OUTPUT BUS PROTECTION SYSTEMS AND METHODS FOR PROGRAMMABLE LO...

MULTIPLE MODE DEVICE IMPLEMENTATION FOR PROGRAMMABLE LOGIC DEVICES

MULTIPLE MODE DEVICE IMPLEMENTATION FOR PROGRAMMABLE LOGIC DEVICES

FLEXIBLE RIPPLE MODE DEVICE IMPLEMENTATION FOR PROGRAMMABLE LOGIC D...

DETERMINISTIC READ BACK AND ERROR DETECTION FOR PROGRAMMABLE LOGIC...

FLEXIBLE RIPPLE MODE DEVICE IMPLEMENTATION FOR PROGRAMMABLE LOGIC D...

SHARED LOGIC FOR MULTIPLE REGISTERS WITH ASYNCHRONOUS INITIALIZATION

MULTIPLE MODE DEVICE IMPLEMENTATION FOR PROGRAMMABLE LOGIC DEVICES

HIGH SPEED COMPLEMENTARY NMOS LUT LOGIC

PVT Compensation Scheme for Output Buffers

Hot-Socket Circuitry

ESD PROTECTION USING SHARED RC TRIGGER

DUAL-PORT SRAM WITH BIT LINE CLAMPING