Bradley A. Burres

Person

Cambridge, MA, US

People

Patents Grantslast 30 patents

Information Patent Grant
VM encryption of block storage with end-to-end data integrity prote...
- Patent number 12,124,619
- Issue date Oct 22, 2024
- Intel Corporation
- Jose Niell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic configuration of input/output controller access lanes
- Patent number 12,079,153
- Issue date Sep 3, 2024
- Intel Corporation
- Balaji Parthasarathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Presentation of direct accessed storage under a logical drive model
- Patent number 12,079,149
- Issue date Sep 3, 2024
- SK Hynix NAND Product Solutions Corp.
- Thomas M. Slaight
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Maintaining storage namespace identifiers for live virtualized exec...
- Patent number 11,941,458
- Issue date Mar 26, 2024
- SK Hynix NAND Product Solutions Corp.
- Jose Niell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic configuration of input/output controller access lanes
- Patent number 11,693,807
- Issue date Jul 4, 2023
- Intel Corporation
- Balaji Parthasarathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Presentation of direct accessed storage under a logical drive model
- Patent number 11,604,746
- Issue date Mar 14, 2023
- SK hynix NAND Product Solutions Corp.
- Thomas M. Slaight
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Presentation of direct accessed storage under a logical drive model
- Patent number 11,449,446
- Issue date Sep 20, 2022
- Intel Corporation
- Thomas M. Slaight
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic configuration of input/output controller access lanes
- Patent number 10,956,351
- Issue date Mar 23, 2021
- Intel Corporation
- Balaji Parthasarathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-core communication acceleration using hardware queue device
- Patent number 10,929,323
- Issue date Feb 23, 2021
- Intel Corporation
- Ren Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technologies for flexible protocol acceleration
- Patent number 10,884,968
- Issue date Jan 5, 2021
- Intel Corporation
- Matthew J. Adiletta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asset protection of integrated circuits during transport
- Patent number 10,628,615
- Issue date Apr 21, 2020
- Intel Corporation
- Ramamurthy Krithivas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-core communication acceleration using hardware queue device
- Patent number 10,445,271
- Issue date Oct 15, 2019
- Intel Corporation
- Ren Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asset protection of integrated circuits during transport
- Patent number 9,996,711
- Issue date Jun 12, 2018
- Intel Corporation
- Ramamurthy Krithivas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Presentation of direct accessed storage under a logical drive model
- Patent number 9,417,821
- Issue date Aug 16, 2016
- Intel Corporation
- Thomas M. Slaight
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Link layer virtualization in SATA controller
- Patent number 9,244,877
- Issue date Jan 26, 2016
- Intel Corporation
- Chengda Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction-set architecture for programmable Cyclic Redundancy Che...
- Patent number 9,047,082
- Issue date Jun 2, 2015
- Intel Corporation
- Vinodh Gopal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Instruction-set architecture for programmable cyclic redundancy che...
- Patent number 8,732,548
- Issue date May 20, 2014
- Intel Corporation
- Vinodh Gopal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Instruction-set architecture for programmable cyclic redundancy che...
- Patent number 8,464,125
- Issue date Jun 11, 2013
- Intel Corporation
- Vinodh Gopal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for performing an authentication after cipher...
- Patent number 8,417,943
- Issue date Apr 9, 2013
- Intel Corporation
- Jaroslaw J. Sydir
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Memory controllers for processor having multiple programmable units
- Patent number 8,316,191
- Issue date Nov 20, 2012
- Intel Corporation
- William R. Wheeler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for scheduling the processing of commands for...
- Patent number 8,065,678
- Issue date Nov 22, 2011
- Intel Corporation
- Jaroslaw J. Sydir
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing an authentication after cipher...
- Patent number 8,041,945
- Issue date Oct 18, 2011
- Intel Corporation
- Jaroslaw J. Sydir
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Techniques for merging tables
- Patent number 7,801,299
- Issue date Sep 21, 2010
- Intel Corporation
- Gunnar Gaubatz
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for performing an authentication after cipher...
- Patent number 7,543,142
- Issue date Jun 2, 2009
- Intel Corporation
- Jaroslaw J. Sydir
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for aligning ciphered data
- Patent number 7,529,924
- Issue date May 5, 2009
- Intel Corporation
- Jaroslaw Sydir
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for scheduling the processing of commands for...
- Patent number 7,512,945
- Issue date Mar 31, 2009
- Intel Corporation
- Jaroslaw J. Sydir
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller for processor having multiple multithreaded progr...
- Patent number 7,424,579
- Issue date Sep 9, 2008
- Intel Corporation
- William R. Wheeler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
SDRAM controller for parallel processor architecture
- Patent number 6,983,350
- Issue date Jan 3, 2006
- Intel Corporation
- William R. Wheeler
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PRESENTATION OF DIRECT ACCESSED STORAGE UNDER A LOGICAL DRIVE MODEL
- Publication number 20240378160
- Publication date Nov 14, 2024
- SK hynix NAND Product Solutions Corp.
- Thomas M. Slaight
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUFFER ALLOCATION
- Publication number 20240211392
- Publication date Jun 27, 2024
- Intel Corporation
- Salma Mirza JOHNSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NETWORK INTERFACE DEVICE AS A COMPUTING PLATFORM
- Publication number 20240012769
- Publication date Jan 11, 2024
- Intel Corporation
- Francesc GUIM BERNAT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC CONFIGURATION OF INPUT/OUTPUT CONTROLLER ACCESS LANES
- Publication number 20230367729
- Publication date Nov 16, 2023
- Intel Corporation
- BALAJI PARTHASARATHY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INPUT/OUTPUT (I/O) VIRTUALIZATION ACCELERATION
- Publication number 20230333921
- Publication date Oct 19, 2023
- Intel Corporation
- Noam ELATI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRESENTATION OF DIRECT ACCESSED STORAGE UNDER A LOGICAL DRIVE MODEL
- Publication number 20230185747
- Publication date Jun 15, 2023
- SK hynix NAND Product Solutions Corp.
- Thomas M. Slaight
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GENERIC APPROACH FOR VIRTUAL DEVICE HYBRID COMPOSITION
- Publication number 20230153143
- Publication date May 18, 2023
- Intel Corporation
- SHAOPENG HE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE ARCHITECTURE FOR STATEFUL DATA PLANE EVENT PROCESSING
- Publication number 20230139762
- Publication date May 4, 2023
- Intel Corporation
- Stephen IBANEZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE TRANSPORT PROTOCOL ARCHITECTURE
- Publication number 20230127722
- Publication date Apr 27, 2023
- Intel Corporation
- Stephen IBANEZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VIRTUAL DEVICE ASSIGNMENT FRAMEWORK
- Publication number 20230108461
- Publication date Apr 6, 2023
- Intel Corporation
- Shaopeng HE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REMOTE DISAGGREGATED INFRASTRUCTURE PROCESSING UNITS (IPUS)
- Publication number 20230096451
- Publication date Mar 30, 2023
- Intel Corporation
- Salma Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEDIA STREAMING ENDPOINT
- Publication number 20220224746
- Publication date Jul 14, 2022
- Intel Corporation
- Yadong LI
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
INITIATOR-SIDE OFFLOAD FOR SCALE-OUT STORAGE
- Publication number 20220114030
- Publication date Apr 14, 2022
- Intel Corporation
- Salma Mirza JOHNSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC CONFIGURATION OF INPUT/OUTPUT CONTROLLER ACCESS LANES
- Publication number 20210326285
- Publication date Oct 21, 2021
- Intel Corporation
- Balaji PARTHASARATHY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VM ENCRYPTION OF BLOCK STORAGE WITH END-TO-END DATA INTEGRITY PROTE...
- Publication number 20210150074
- Publication date May 20, 2021
- Jose Niell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRESENTATION OF DIRECT ACCESSED STORAGE UNDER A LOGICAL DRIVE MODEL
- Publication number 20200349100
- Publication date Nov 5, 2020
- Intel Corporation
- Thomas M. Slaight
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MAINTAINING STORAGE NAMESPACE IDENTIFIERS FOR LIVE VIRTUALIZED EXEC...
- Publication number 20200278893
- Publication date Sep 3, 2020
- Intel Corporation
- Jose NIELL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-LEVEL MEMORY WITH IMPROVED MEMORY SIDE CACHE IMPLEMENTATION
- Publication number 20200125495
- Publication date Apr 23, 2020
- Intel Corporation
- Duane E. GALBI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARED MEMORY SPACE AMONG DEVICES
- Publication number 20200104275
- Publication date Apr 2, 2020
- Intel Corporation
- Sujoy SEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGIES FOR FLEXIBLE PROTOCOL ACCELERATION
- Publication number 20200073846
- Publication date Mar 5, 2020
- Matthew J. Adiletta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-CORE COMMUNICATION ACCELERATION USING HARDWARE QUEUE DEVICE
- Publication number 20200042479
- Publication date Feb 6, 2020
- Intel Corporation
- Ren Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC CONFIGURATION OF INPUT/OUTPUT CONTROLLER ACCESS LANES
- Publication number 20200004713
- Publication date Jan 2, 2020
- Intel Corporation
- BALAJI PARTHASARATHY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASSET PROTECTION OF INTEGRATED CIRCUITS DURING TRANSPORT
- Publication number 20190087610
- Publication date Mar 21, 2019
- Intel Corporation
- Ramamurthy Krithivas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC CONFIGURATION OF INPUT/OUTPUT CONTROLLER ACCESS LANES
- Publication number 20180081847
- Publication date Mar 22, 2018
- Intel Corporation
- BALAJI PARTHASARATHY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-CORE COMMUNICATION ACCELERATION USING HARDWARE QUEUE DEVICE
- Publication number 20170192921
- Publication date Jul 6, 2017
- Ren Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASSET PROTECTION OF INTEGRATED CIRCUITS DURING TRANSPORT
- Publication number 20170124358
- Publication date May 4, 2017
- Ramamurthy Krithivas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRESENTATION OF DIRECT ACCESSED STORAGE UNDER A LOGICAL DRIVE MODEL
- Publication number 20160335208
- Publication date Nov 17, 2016
- Intel Corporation
- Thomas M. Slaight
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LINK LAYER VIRTUALIZATION IN SATA CONTROLLER
- Publication number 20140281072
- Publication date Sep 18, 2014
- CHENGDA YANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION-SET ARCHITECTURE FOR PROGRAMMABLE CYCLIC REDUNDANCY CHE...
- Publication number 20140229807
- Publication date Aug 14, 2014
- VINODH GOPAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRESENTATION OF DIRECT ACCESSED STORAGE UNDER A LOGICAL DRIVE MODEL
- Publication number 20140189212
- Publication date Jul 3, 2014
- Thomas M. Slaight
- G06 - COMPUTING CALCULATING COUNTING

Bradley A. Burres

Person

Patents Grantslast 30 patents

VM encryption of block storage with end-to-end data integrity prote...

Dynamic configuration of input/output controller access lanes

Presentation of direct accessed storage under a logical drive model

Maintaining storage namespace identifiers for live virtualized exec...

Dynamic configuration of input/output controller access lanes

Presentation of direct accessed storage under a logical drive model

Presentation of direct accessed storage under a logical drive model

Dynamic configuration of input/output controller access lanes

Multi-core communication acceleration using hardware queue device

Technologies for flexible protocol acceleration

Asset protection of integrated circuits during transport

Multi-core communication acceleration using hardware queue device

Asset protection of integrated circuits during transport

Presentation of direct accessed storage under a logical drive model

Link layer virtualization in SATA controller

Instruction-set architecture for programmable Cyclic Redundancy Che...

Instruction-set architecture for programmable cyclic redundancy che...

Instruction-set architecture for programmable cyclic redundancy che...

Method and apparatus for performing an authentication after cipher...

Memory controllers for processor having multiple programmable units

Method and apparatus for scheduling the processing of commands for...

Method and apparatus for performing an authentication after cipher...

Techniques for merging tables

Method and apparatus for performing an authentication after cipher...

Method and apparatus for aligning ciphered data

Method and apparatus for scheduling the processing of commands for...

Memory controller for processor having multiple multithreaded progr...

SDRAM controller for parallel processor architecture

Patents Applicationslast 30 patents

PRESENTATION OF DIRECT ACCESSED STORAGE UNDER A LOGICAL DRIVE MODEL

BUFFER ALLOCATION

NETWORK INTERFACE DEVICE AS A COMPUTING PLATFORM

DYNAMIC CONFIGURATION OF INPUT/OUTPUT CONTROLLER ACCESS LANES

INPUT/OUTPUT (I/O) VIRTUALIZATION ACCELERATION

PRESENTATION OF DIRECT ACCESSED STORAGE UNDER A LOGICAL DRIVE MODEL

GENERIC APPROACH FOR VIRTUAL DEVICE HYBRID COMPOSITION

PROGRAMMABLE ARCHITECTURE FOR STATEFUL DATA PLANE EVENT PROCESSING

PROGRAMMABLE TRANSPORT PROTOCOL ARCHITECTURE

VIRTUAL DEVICE ASSIGNMENT FRAMEWORK

REMOTE DISAGGREGATED INFRASTRUCTURE PROCESSING UNITS (IPUS)

MEDIA STREAMING ENDPOINT

INITIATOR-SIDE OFFLOAD FOR SCALE-OUT STORAGE

DYNAMIC CONFIGURATION OF INPUT/OUTPUT CONTROLLER ACCESS LANES

VM ENCRYPTION OF BLOCK STORAGE WITH END-TO-END DATA INTEGRITY PROTE...

PRESENTATION OF DIRECT ACCESSED STORAGE UNDER A LOGICAL DRIVE MODEL

MAINTAINING STORAGE NAMESPACE IDENTIFIERS FOR LIVE VIRTUALIZED EXEC...

MULTI-LEVEL MEMORY WITH IMPROVED MEMORY SIDE CACHE IMPLEMENTATION

SHARED MEMORY SPACE AMONG DEVICES

TECHNOLOGIES FOR FLEXIBLE PROTOCOL ACCELERATION

MULTI-CORE COMMUNICATION ACCELERATION USING HARDWARE QUEUE DEVICE

DYNAMIC CONFIGURATION OF INPUT/OUTPUT CONTROLLER ACCESS LANES

ASSET PROTECTION OF INTEGRATED CIRCUITS DURING TRANSPORT

DYNAMIC CONFIGURATION OF INPUT/OUTPUT CONTROLLER ACCESS LANES

MULTI-CORE COMMUNICATION ACCELERATION USING HARDWARE QUEUE DEVICE

ASSET PROTECTION OF INTEGRATED CIRCUITS DURING TRANSPORT

PRESENTATION OF DIRECT ACCESSED STORAGE UNDER A LOGICAL DRIVE MODEL

LINK LAYER VIRTUALIZATION IN SATA CONTROLLER

INSTRUCTION-SET ARCHITECTURE FOR PROGRAMMABLE CYCLIC REDUNDANCY CHE...

PRESENTATION OF DIRECT ACCESSED STORAGE UNDER A LOGICAL DRIVE MODEL