Bradley J. Garni

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Bypass system and method that mimics clock to data memory read timing
- Patent number 9,263,100
- Issue date Feb 16, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Bradley J. Garni
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit having low power mode voltage regulator
- Patent number 8,319,548
- Issue date Nov 27, 2012
- FREESCALE SEMICONDUCTOR, INC.
- Ravindraraj Ramaraju
- G05 - CONTROLLING REGULATING
Information Patent Grant
MRAM architecture with electrically isolated read and write circuitry
- Patent number 7,154,772
- Issue date Dec 26, 2006
- FREESCALE SEMICONDUCTOR, INC.
- Joseph J. Nahas
- G11 - INFORMATION STORAGE
Information Patent Grant
MRAM sense amplifier having a precharge circuit and method for sensing
- Patent number 7,038,959
- Issue date May 2, 2006
- FREESCALE SEMICONDUCTOR, INC.
- Bradley J. Garni
- G11 - INFORMATION STORAGE
Information Patent Grant
MRAM and methods for reading the MRAM
- Patent number 6,909,631
- Issue date Jun 21, 2005
- FREESCALE SEMICONDUCTOR, INC.
- Mark A. Durlam
- G11 - INFORMATION STORAGE
Information Patent Grant
MRAM architecture with electrically isolated read and write circuitry
- Patent number 6,903,964
- Issue date Jun 7, 2005
- FREESCALE SEMICONDUCTOR, INC.
- Joseph J. Nahas
- G11 - INFORMATION STORAGE
Information Patent Grant
Accelerated life test of MRAM cells
- Patent number 6,894,937
- Issue date May 17, 2005
- FREESCALE SEMICONDUCTOR, INC.
- Bradley J. Garni
- G11 - INFORMATION STORAGE
Information Patent Grant
MRAM architecture
- Patent number 6,888,743
- Issue date May 3, 2005
- FREESCALE SEMICONDUCTOR, INC.
- Mark A. Durlam
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense amplifier and method for performing a read operation in a MRAM
- Patent number 6,760,266
- Issue date Jul 6, 2004
- FREESCALE SEMICONDUCTOR, INC.
- Bradley J. Garni
- G11 - INFORMATION STORAGE
Information Patent Grant
Technique for sensing the state of a magneto-resistive random acces...
- Patent number 6,738,303
- Issue date May 18, 2004
- Motorola, Inc.
- Chitra K. Subramanian
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense amplifier bias circuit for a memory having at least two disti...
- Patent number 6,700,814
- Issue date Mar 2, 2004
- Motorola, Inc.
- Joseph J. Nahas
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory having write current ramp rate control
- Patent number 6,657,889
- Issue date Dec 2, 2003
- Motorola, Inc.
- Chitra K. Subramanian
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense amplifier incorporating a symmetric midpoint reference
- Patent number 6,621,729
- Issue date Sep 16, 2003
- Motorola, Inc.
- Bradley J. Garni
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense amplifier for a memory having at least two distinct resistanc...
- Patent number 6,600,690
- Issue date Jul 29, 2003
- Motorola, Inc.
- Joseph J. Nahas
- G11 - INFORMATION STORAGE
Information Patent Grant
Three input sense amplifier and method of operation
- Patent number 6,580,298
- Issue date Jun 17, 2003
- Motorola, Inc.
- Chitra K. Subramanian
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and circuitry for identifying weak bits in an MRAM
- Patent number 6,538,940
- Issue date Mar 25, 2003
- Motorola, Inc.
- Joseph J. Nahas
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
BYPASS SYSTEM AND METHOD THAT MIMICS CLOCK TO DATA MEMORY READ TIMING
- Publication number 20150155017
- Publication date Jun 4, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Bradley J. Garni
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUIT HAVING LOW POWER MODE VOLTAGE RETULATOR
- Publication number 20100207688
- Publication date Aug 19, 2010
- RAVINDRARAJ RAMARAJU
- G05 - CONTROLLING REGULATING
Information Patent Application
MRAM SENSE AMPLIFIER HAVING A PRECHARGE CIRCUIT AND METHOD FOR SENSING
- Publication number 20060062066
- Publication date Mar 23, 2006
- Bradley J. Garni
- G11 - INFORMATION STORAGE
Information Patent Application
MRAM architecture with electrically isolated read and write circuitry
- Publication number 20050152183
- Publication date Jul 14, 2005
- Joseph J. Nahas
- G11 - INFORMATION STORAGE
Information Patent Application
ACCELERATED LIFE TEST OF MRAM CELLS
- Publication number 20050068815
- Publication date Mar 31, 2005
- Bradley J. Garni
- G11 - INFORMATION STORAGE
Information Patent Application
MRAM and methods for reading the MRAM
- Publication number 20040125649
- Publication date Jul 1, 2004
- Mark A. Durlam
- G11 - INFORMATION STORAGE
Information Patent Application
MRAM architecture
- Publication number 20040125646
- Publication date Jul 1, 2004
- Mark A. Durlam
- G11 - INFORMATION STORAGE
Information Patent Application
TECHNIQUE FOR SENSING THE STATE OF A MAGNETO-RESISTIVE RANDOM ACCES...
- Publication number 20040100845
- Publication date May 27, 2004
- Chitra K. Subramanian
- G11 - INFORMATION STORAGE
Information Patent Application
Circuit and method for reading a toggle memory cell
- Publication number 20040008536
- Publication date Jan 15, 2004
- Bradley J. Garni
- G11 - INFORMATION STORAGE
Information Patent Application
Sense amplifier and method for performing a read operation in a MRAM
- Publication number 20040001383
- Publication date Jan 1, 2004
- Bradley J. Garni
- G11 - INFORMATION STORAGE
Information Patent Application
MRAM architecture with electrically isolated read and write circuitry
- Publication number 20040001358
- Publication date Jan 1, 2004
- Joseph J. Nahas
- G11 - INFORMATION STORAGE

Bradley J. Garni

Person

Patents Grantslast 30 patents

Bypass system and method that mimics clock to data memory read timing

Integrated circuit having low power mode voltage regulator

MRAM architecture with electrically isolated read and write circuitry

MRAM sense amplifier having a precharge circuit and method for sensing

MRAM and methods for reading the MRAM

MRAM architecture with electrically isolated read and write circuitry

Accelerated life test of MRAM cells

MRAM architecture

Sense amplifier and method for performing a read operation in a MRAM

Technique for sensing the state of a magneto-resistive random acces...

Sense amplifier bias circuit for a memory having at least two disti...

Memory having write current ramp rate control

Sense amplifier incorporating a symmetric midpoint reference

Sense amplifier for a memory having at least two distinct resistanc...

Three input sense amplifier and method of operation

Method and circuitry for identifying weak bits in an MRAM

Patents Applicationslast 30 patents

BYPASS SYSTEM AND METHOD THAT MIMICS CLOCK TO DATA MEMORY READ TIMING

INTEGRATED CIRCUIT HAVING LOW POWER MODE VOLTAGE RETULATOR

MRAM SENSE AMPLIFIER HAVING A PRECHARGE CIRCUIT AND METHOD FOR SENSING

MRAM architecture with electrically isolated read and write circuitry

ACCELERATED LIFE TEST OF MRAM CELLS

MRAM and methods for reading the MRAM

MRAM architecture

TECHNIQUE FOR SENSING THE STATE OF A MAGNETO-RESISTIVE RANDOM ACCES...

Circuit and method for reading a toggle memory cell

Sense amplifier and method for performing a read operation in a MRAM

MRAM architecture with electrically isolated read and write circuitry