Brett W. Coon

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Dynamic loading of radar unit configuration data based on changing...
- Patent number 12,196,883
- Issue date Jan 14, 2025
- Waymo LLC
- Kevin Duncklee
- G01 - MEASURING TESTING
Information Patent Grant
Signal processing for near-field radar
- Patent number 12,007,498
- Issue date Jun 11, 2024
- Waymo LLC
- Timothy Campbell
- G01 - MEASURING TESTING
Information Patent Grant
Dynamic loading of radar unit configuration data based on changing...
- Patent number 11,796,633
- Issue date Oct 24, 2023
- Waymo LLC
- Kevin Duncklee
- G01 - MEASURING TESTING
Information Patent Grant
Signal processing for near-field radar
- Patent number 10,866,305
- Issue date Dec 15, 2020
- Waymo LLC
- Timothy Campbell
- G01 - MEASURING TESTING
Information Patent Grant
Instructions for managing a parallel cache hierarchy
- Patent number 10,365,930
- Issue date Jul 30, 2019
- NVIDIA Corporation
- John R. Nickolls
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable graphics processor for multithreaded execution of prog...
- Patent number 10,217,184
- Issue date Feb 26, 2019
- NVIDIA Corporation
- John Erik Lindholm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache operations and policies for a multi-threaded client
- Patent number 9,952,977
- Issue date Apr 24, 2018
- NVIDIA Corporation
- Steven James Heinrich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cooperative thread array reduction and scan operations
- Patent number 9,830,197
- Issue date Nov 28, 2017
- NVIDIA Corporation
- Brian Fahs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable graphics processor for multithreaded execution of prog...
- Patent number 9,659,339
- Issue date May 23, 2017
- NVIDIA Corporation
- John Erik Lindholm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Indirect function call instructions in a synchronous parallel threa...
- Patent number 9,639,365
- Issue date May 2, 2017
- NVIDIA Corporation
- Brett W. Coon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instructions for managing a parallel cache hierarchy
- Patent number 9,639,479
- Issue date May 2, 2017
- NVIDIA Corporation
- John R. Nickolls
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cooperative thread array reduction and scan operations
- Patent number 9,417,875
- Issue date Aug 16, 2016
- NVIDIA Corporation
- Brian Fahs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coalescing memory barrier operations across multiple parallel threads
- Patent number 9,223,578
- Issue date Dec 29, 2015
- NVIDIA Corporation
- John R. Nickolls
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Credit-based streaming multiprocessor warp scheduling
- Patent number 9,189,242
- Issue date Nov 17, 2015
- NVIDIA Corporation
- John Erik Lindholm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable graphics processor for multithreaded execution of prog...
- Patent number 8,860,737
- Issue date Oct 14, 2014
- NVIDIA Corporation
- John Erik Lindholm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient implementation of arrays of structures on SIMT and SIMD a...
- Patent number 8,751,771
- Issue date Jun 10, 2014
- NVIDIA Corporation
- Brian Fahs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Thread group scheduler for computing on a parallel thread processor
- Patent number 8,732,713
- Issue date May 20, 2014
- NVIDIA Corporation
- Brett W. Coon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and method for managing divergent threads in a SIMD archite...
- Patent number 8,667,256
- Issue date Mar 4, 2014
- NVIDIA Corporation
- Brett W. Coon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared single-access memory with management of multiple parallel re...
- Patent number 8,645,638
- Issue date Feb 4, 2014
- NVIDIA Corporation
- Brett W. Coon
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Configurable cache for multiple clients
- Patent number 8,595,425
- Issue date Nov 26, 2013
- NVIDIA Corporation
- Alexander L. Minkin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Support for non-local returns in parallel thread SIMD engine
- Patent number 8,572,355
- Issue date Oct 29, 2013
- NVIDIA Corporation
- Guillermo Juan Rozas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method of instruction modification
- Patent number 8,549,266
- Issue date Oct 1, 2013
- John P. Banning
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cooperative thread array reduction and scan operations
- Patent number 8,539,204
- Issue date Sep 17, 2013
- NVIDIA Corporation
- Brian Fahs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Trap handler architecture for a parallel processing unit
- Patent number 8,522,000
- Issue date Aug 27, 2013
- NVIDIA Corporation
- Michael C. Shebanow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipeline replay support for multicycle operations
- Patent number 8,516,224
- Issue date Aug 20, 2013
- Brett Coon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable graphics processor for multithreaded execution of prog...
- Patent number 8,405,665
- Issue date Mar 26, 2013
- NVIDIA Corporation
- John Erik Lindholm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Lock mechanism to enable atomic updates to shared memory
- Patent number 8,375,176
- Issue date Feb 12, 2013
- NVIDIA Corporation
- Brett W. Coon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Maximized memory throughput on parallel processing devices
- Patent number 8,327,123
- Issue date Dec 4, 2012
- NVIDIA Corporation
- Norbert Juffa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Indirect function call instructions in a synchronous parallel threa...
- Patent number 8,312,254
- Issue date Nov 13, 2012
- NVIDIA Corporation
- Brett W. Coon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Unified addressing and instructions for accessing parallel memory s...
- Patent number 8,271,763
- Issue date Sep 18, 2012
- NVIDIA Corporation
- John R. Nickolls
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Signal Processing for Near-Field Radar
- Publication number 20240295629
- Publication date Sep 5, 2024
- WAYMO LLC
- Timothy Campbell
- G01 - MEASURING TESTING
Information Patent Application
Dynamic Loading of Radar Unit Configuration Data Based on Changing...
- Publication number 20240004029
- Publication date Jan 4, 2024
- WAYMO LLC
- Kevin Duncklee
- G01 - MEASURING TESTING
Information Patent Application
Dynamic Loading of Radar Unit Configuration Data Based on Changing...
- Publication number 20210181302
- Publication date Jun 17, 2021
- WAYMO LLC
- Kevin Duncklee
- G01 - MEASURING TESTING
Information Patent Application
Signal Processing for Near-Field Radar
- Publication number 20210080539
- Publication date Mar 18, 2021
- WAYMO LLC
- Timothy Campbell
- G01 - MEASURING TESTING
Information Patent Application
PROGRAMMABLE GRAPHICS PROCESSOR FOR MULTITHREADED EXECUTION OF PROG...
- Publication number 20170256022
- Publication date Sep 7, 2017
- NVIDIA Corporation
- John Erik LINDHOLM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTIONS FOR MANAGING A PARALLEL CACHE HIERARCHY
- Publication number 20170235581
- Publication date Aug 17, 2017
- NVIDIA Corporation
- John R. NICKOLLS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COOPERATIVE THREAD ARRAY REDUCTION AND SCAN OPERATIONS
- Publication number 20160357560
- Publication date Dec 8, 2016
- NVIDIA Corporation
- Brian FAHS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE GRAPHICS PROCESSOR FOR MULTITHREADED EXECUTION OF PROG...
- Publication number 20160300319
- Publication date Oct 13, 2016
- NVIDIA Corporation
- John Erik LINDHOLM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE GRAPHICS PROCESSOR FOR MULTITHREADED EXECUTION OF PROG...
- Publication number 20140285500
- Publication date Sep 25, 2014
- NVIDIA Corporation
- John Erik LINDHOLM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COOPERATIVE THREAD ARRAY REDUCTION AND SCAN OPERATIONS
- Publication number 20140019724
- Publication date Jan 16, 2014
- NVIDIA Corporation
- Brian FAHS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INDIRECT FUNCTION CALL INSTRUCTIONS IN A SYNCHRONOUS PARALLEL THREA...
- Publication number 20130138926
- Publication date May 30, 2013
- NVIDIA Corporation
- Brett W. Coon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARED SINGLE-ACCESS MEMORY WITH MANAGEMENT OF MULTIPLE PARALLEL RE...
- Publication number 20120221808
- Publication date Aug 30, 2012
- NVIDIA Corporation
- Brett W. Coon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE GRAPHICS PROCESSOR FOR MULTITHREADED EXECUTION OF PROG...
- Publication number 20120218267
- Publication date Aug 30, 2012
- John Erik Lindholm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PIPELINE REPLAY SUPPORT FOR MULTICYCLE OPERATIONS
- Publication number 20120166768
- Publication date Jun 28, 2012
- Brett Coon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREAD GROUP SCHEDULER FOR COMPUTING ON A PARALLEL THREAD PROCESSOR
- Publication number 20120110586
- Publication date May 3, 2012
- Brett W. Coon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT IMPLEMENTATION OF ARRAYS OF STRUCTURES ON SIMT AND SIMD A...
- Publication number 20120089792
- Publication date Apr 12, 2012
- Brian FAHS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOCK MECHANISM TO ENABLE ATOMIC UPDATES TO SHARED MEMORY
- Publication number 20120036329
- Publication date Feb 9, 2012
- Brett W. Coon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL PROCESSOR ARRAY
- Publication number 20120026175
- Publication date Feb 2, 2012
- NVIDIA Corporation
- John Erik Lindholm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARED SINGLE ACCESS MEMORY WITH MANAGEMENT OF MULTIPLE PARALLEL RE...
- Publication number 20110252204
- Publication date Oct 13, 2011
- NVIDIA Corporation
- Brett W. Coon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD OF INSTRUCTION MODIFICATION
- Publication number 20110238961
- Publication date Sep 29, 2011
- John Banning
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MAXIMIZED MEMORY THROUGHPUT ON PARALLEL PROCESSING DEVICES
- Publication number 20110173414
- Publication date Jul 14, 2011
- NVIDIA Corporation
- Norbert Juffa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COOPERATIVE THREAD ARRAY REDUCTION AND SCAN OPERATIONS
- Publication number 20110078417
- Publication date Mar 31, 2011
- Brian FAHS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Support for Non-Local Returns in Parallel Thread SIMD Engine
- Publication number 20110078418
- Publication date Mar 31, 2011
- Guillermo Juan Rozas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Unified Addressing and Instructions for Accessing Parallel Memory S...
- Publication number 20110078406
- Publication date Mar 31, 2011
- John R. Nickolls
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURABLE CACHE FOR MULTIPLE CLIENTS
- Publication number 20110078367
- Publication date Mar 31, 2011
- Alexander L. Minkin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cache Operations and Policies For A Multi-Threaded Client
- Publication number 20110078381
- Publication date Mar 31, 2011
- Steven James HEINRICH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COALESCING MEMORY BARRIER OPERATIONS ACROSS MULTIPLE PARALLEL THREADS
- Publication number 20110078692
- Publication date Mar 31, 2011
- John R. NICKOLLS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRAP HANDLER ARCHITECTURE FOR A PARALLEL PROCESSING UNIT
- Publication number 20110078427
- Publication date Mar 31, 2011
- Michael C. Shebanow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Credit-Based Streaming Multiprocessor Warp Scheduling
- Publication number 20110072244
- Publication date Mar 24, 2011
- John Erik Lindholm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTIONS FOR MANAGING A PARALLEL CACHE HIERARCHY
- Publication number 20110072213
- Publication date Mar 24, 2011
- John R. NICKOLLS
- G06 - COMPUTING CALCULATING COUNTING

Brett W. Coon

Person

Patents Grantslast 30 patents

Dynamic loading of radar unit configuration data based on changing...

Signal processing for near-field radar

Dynamic loading of radar unit configuration data based on changing...

Signal processing for near-field radar

Instructions for managing a parallel cache hierarchy

Programmable graphics processor for multithreaded execution of prog...

Cache operations and policies for a multi-threaded client

Cooperative thread array reduction and scan operations

Programmable graphics processor for multithreaded execution of prog...

Indirect function call instructions in a synchronous parallel threa...

Instructions for managing a parallel cache hierarchy

Cooperative thread array reduction and scan operations

Coalescing memory barrier operations across multiple parallel threads

Credit-based streaming multiprocessor warp scheduling

Programmable graphics processor for multithreaded execution of prog...

Efficient implementation of arrays of structures on SIMT and SIMD a...

Thread group scheduler for computing on a parallel thread processor

Systems and method for managing divergent threads in a SIMD archite...

Shared single-access memory with management of multiple parallel re...

Configurable cache for multiple clients

Support for non-local returns in parallel thread SIMD engine

System and method of instruction modification

Cooperative thread array reduction and scan operations

Trap handler architecture for a parallel processing unit

Pipeline replay support for multicycle operations

Programmable graphics processor for multithreaded execution of prog...

Lock mechanism to enable atomic updates to shared memory

Maximized memory throughput on parallel processing devices

Indirect function call instructions in a synchronous parallel threa...

Unified addressing and instructions for accessing parallel memory s...

Patents Applicationslast 30 patents

Signal Processing for Near-Field Radar

Dynamic Loading of Radar Unit Configuration Data Based on Changing...

Dynamic Loading of Radar Unit Configuration Data Based on Changing...

Signal Processing for Near-Field Radar

PROGRAMMABLE GRAPHICS PROCESSOR FOR MULTITHREADED EXECUTION OF PROG...

INSTRUCTIONS FOR MANAGING A PARALLEL CACHE HIERARCHY

COOPERATIVE THREAD ARRAY REDUCTION AND SCAN OPERATIONS

PROGRAMMABLE GRAPHICS PROCESSOR FOR MULTITHREADED EXECUTION OF PROG...

PROGRAMMABLE GRAPHICS PROCESSOR FOR MULTITHREADED EXECUTION OF PROG...

COOPERATIVE THREAD ARRAY REDUCTION AND SCAN OPERATIONS

INDIRECT FUNCTION CALL INSTRUCTIONS IN A SYNCHRONOUS PARALLEL THREA...

SHARED SINGLE-ACCESS MEMORY WITH MANAGEMENT OF MULTIPLE PARALLEL RE...

PROGRAMMABLE GRAPHICS PROCESSOR FOR MULTITHREADED EXECUTION OF PROG...

PIPELINE REPLAY SUPPORT FOR MULTICYCLE OPERATIONS

THREAD GROUP SCHEDULER FOR COMPUTING ON A PARALLEL THREAD PROCESSOR

EFFICIENT IMPLEMENTATION OF ARRAYS OF STRUCTURES ON SIMT AND SIMD A...

LOCK MECHANISM TO ENABLE ATOMIC UPDATES TO SHARED MEMORY

HIERARCHICAL PROCESSOR ARRAY

SHARED SINGLE ACCESS MEMORY WITH MANAGEMENT OF MULTIPLE PARALLEL RE...

SYSTEM AND METHOD OF INSTRUCTION MODIFICATION

MAXIMIZED MEMORY THROUGHPUT ON PARALLEL PROCESSING DEVICES

COOPERATIVE THREAD ARRAY REDUCTION AND SCAN OPERATIONS

Support for Non-Local Returns in Parallel Thread SIMD Engine

Unified Addressing and Instructions for Accessing Parallel Memory S...

CONFIGURABLE CACHE FOR MULTIPLE CLIENTS

Cache Operations and Policies For A Multi-Threaded Client

COALESCING MEMORY BARRIER OPERATIONS ACROSS MULTIPLE PARALLEL THREADS

TRAP HANDLER ARCHITECTURE FOR A PARALLEL PROCESSING UNIT

Credit-Based Streaming Multiprocessor Warp Scheduling

INSTRUCTIONS FOR MANAGING A PARALLEL CACHE HIERARCHY