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Brian Foutz
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Silver Spring, MD, US
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Patents Grants
last 30 patents
Information
Patent Grant
Systems and methods for scan chain stitching
Patent number
12,007,440
Issue date
Jun 11, 2024
Cadence Design Systems, Inc.
Puneet Arora
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Test-point flop sharing with improved testability in a circuit design
Patent number
11,947,887
Issue date
Apr 2, 2024
Cadence Design Systems, Inc.
Krishna Chakravadhanula
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Method to improve testability using 2-dimensional exclusive or (XOR...
Patent number
10,955,470
Issue date
Mar 23, 2021
Cadence Design Systems, Inc.
Brian Edward Foutz
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Low-power shift with clock staggering
Patent number
10,775,435
Issue date
Sep 15, 2020
Cadence Design Systems, Inc.
Christos Papameletis
G01 - MEASURING TESTING
Information
Patent Grant
Method for optimally connecting scan segments in two-dimensional co...
Patent number
10,761,131
Issue date
Sep 1, 2020
Cadence Design Systems, Inc.
Christos Papameletis
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
2D compression-based low power ATPG
Patent number
10,551,435
Issue date
Feb 4, 2020
Cadence Design Systems, Inc.
Nitin Parimi
G01 - MEASURING TESTING
Information
Patent Grant
SoC top-level XOR compactor design to efficiently test and diagnose...
Patent number
10,331,506
Issue date
Jun 25, 2019
Cadence Design Systems, Inc.
Vivek Chickermane
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Method and system for construction of a highly efficient and predic...
Patent number
9,817,069
Issue date
Nov 14, 2017
Cadence Design Systems, Inc.
Steev Wilcox
G01 - MEASURING TESTING
Information
Patent Grant
Method and system for improving efficiency of sequential test compr...
Patent number
9,817,068
Issue date
Nov 14, 2017
Cadence Design Systems, Inc.
Vivek Chickermane
G01 - MEASURING TESTING
Information
Patent Grant
Method and system for improving efficiency of XOR-based test compre...
Patent number
9,606,179
Issue date
Mar 28, 2017
Cadence Design Systems, Inc.
Paul Alexander Cunningham
G01 - MEASURING TESTING
Information
Patent Grant
Method for using XOR trees for physically efficient scan compressio...
Patent number
9,513,335
Issue date
Dec 6, 2016
Cadence Design Systems, Inc.
Steev Wilcox
G01 - MEASURING TESTING
Information
Patent Grant
Method for dividing testable logic into a two-dimensional grid for...
Patent number
9,470,755
Issue date
Oct 18, 2016
Cadence Design Systems, Inc.
Brian Edward Foutz
G01 - MEASURING TESTING
Information
Patent Grant
Elastic compression-optimizing tester bandwidth with compressed tes...
Patent number
9,470,754
Issue date
Oct 18, 2016
Cadence Design Systems, Inc.
Vivek Chickermane
G01 - MEASURING TESTING
Information
Patent Grant
Method for using sequential decompression logic for VLSI test in a...
Patent number
9,470,756
Issue date
Oct 18, 2016
Cadence Design Systems, Inc.
Steev Wilcox
G01 - MEASURING TESTING
Information
Patent Grant
Scan testing architectures for power-shutoff aware systems
Patent number
8,001,433
Issue date
Aug 16, 2011
Cadence Design Systems, Inc.
Sandeep Bhatia
G01 - MEASURING TESTING
Information
Patent Grant
Distributed test compression for integrated circuits
Patent number
7,979,764
Issue date
Jul 12, 2011
Cadence Design Systems, Inc.
Brian Foutz
G01 - MEASURING TESTING
Information
Patent Grant
Design-For-testability planner
Patent number
7,926,012
Issue date
Apr 12, 2011
Cadence Design Systems, Inc.
Nitin Parimi
G06 - COMPUTING CALCULATING COUNTING
Patents Applications
last 30 patents
Information
Patent Application
DISTRIBUTED TEST COMPRESSION FOR INTEGRATED CIRCUITS
Publication number
20090119559
Publication date
May 7, 2009
Cadence Design Systems, Inc.
Brian Foutz
G06 - COMPUTING CALCULATING COUNTING