Brian Gaudet

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Systems and methods for converting a P packet/cycle datapath to a Q...
- Patent number 8,098,655
- Issue date Jan 17, 2012
- Juniper Networks, Inc.
- Brian Gaudet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for limiting the rates of data to/from a buffer
- Patent number 8,014,281
- Issue date Sep 6, 2011
- Juniper Networks, Inc.
- Raymond Marcelino Manese Lim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for routing data in a network device
- Patent number 7,936,759
- Issue date May 3, 2011
- Juniper Networks, Inc.
- Kong Kritayakirana
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Systems and methods for limiting the rates of data to/from a buffer
- Patent number 7,630,309
- Issue date Dec 8, 2009
- Juniper Networks, Inc.
- Raymond Marcelino Manese Lim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for converting a P packet/cycle datapath to a Q...
- Patent number 7,583,663
- Issue date Sep 1, 2009
- Juniper Networks, Inc.
- Brian Gaudet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for routing data in a network device
- Patent number 7,167,476
- Issue date Jan 23, 2007
- Juniper Networks, Inc.
- Kong Kritayakirana
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Systems and methods for limiting the rates of data to/from a buffer
- Patent number 7,106,696
- Issue date Sep 12, 2006
- Juniper Networks, Inc.
- Raymond Marcelino Manese Lim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for converting a P packet/cycle datapath to a Q...
- Patent number 7,103,038
- Issue date Sep 5, 2006
- Juniper Networks, Inc.
- Brian Gaudet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scaleable gap insertion in a data link
- Patent number 6,970,956
- Issue date Nov 29, 2005
- Juniper Networks, Inc.
- Brian Gaudet
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Systems and methods for removing intrapacket gaps from streams of d...
- Patent number 6,952,738
- Issue date Oct 4, 2005
- Juniper Networks, Inc.
- Brian Gaudet
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for equalizing propagation delay
- Patent number 6,529,571
- Issue date Mar 4, 2003
- National Semiconductor Corporation
- Brian C. Gaudet
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
High speed network switch bus clock
- Patent number 6,480,498
- Issue date Nov 12, 2002
- National Semiconductor Corporation
- Brian Gaudet
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
High-speed network switch bus
- Patent number 6,421,348
- Issue date Jul 16, 2002
- National Semiconductor Corporation
- Brian Gaudet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
10/100 mb clock recovery architecture for switches, repeaters and m...
- Patent number 6,285,726
- Issue date Sep 4, 2001
- National Semiconductor Corporation
- Brian Gaudet
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Adaptive differential ADC architecture
- Patent number 6,229,469
- Issue date May 8, 2001
- Agere Systems Guardian Corp.
- Brian C. Gaudet
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Ground bounce control using DLL to optimize output stage di/dt usin...
- Patent number 6,154,083
- Issue date Nov 28, 2000
- National Semiconductor Corporation
- Brian Gaudet
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
DLL calibrated phase multiplexer and interpolator
- Patent number 6,121,808
- Issue date Sep 19, 2000
- National Semiconductor Corporation
- Brian Gaudet
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
DLL calibrated switched current delay interpolator
- Patent number 6,094,082
- Issue date Jul 25, 2000
- National Semiconductor Corporation
- Brian Gaudet
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and method to adaptively equalize duty cycle distortion
- Patent number 6,088,415
- Issue date Jul 11, 2000
- National Semiconductor Corporation
- Brian Gaudet
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Delay locked loop (DLL) based clock synthesis
- Patent number 6,037,812
- Issue date Mar 14, 2000
- National Semiconductor Corporation
- Brian Gaudet
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
1000 mb phase picker clock recovery architecture using interleaved...
- Patent number 6,035,409
- Issue date Mar 7, 2000
- National Semiconductor Corporation
- Brian Gaudet
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for adaptive equalization using feedback indic...
- Patent number 6,002,717
- Issue date Dec 14, 1999
- National Semiconductor Corporation
- Brian Gaudet
- G02 - OPTICS
Information Patent Grant
Scan flip-flop that holds state during shifting
- Patent number 5,633,606
- Issue date May 27, 1997
- National Semiconductor Corporation
- Brian C. Gaudet
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
SYSTEMS AND METHODS FOR ROUTING DATA IN A NETWORK DEVICE
- Publication number 20110173520
- Publication date Jul 14, 2011
- Juniper Networks, Inc.
- Kong KRITAYAKIRANA
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SYSTEMS AND METHODS FOR ROUTING DATA IN A NETWORK DEVICE
- Publication number 20070174728
- Publication date Jul 26, 2007
- Juniper Networks, Inc.
- Kong KRITAYAKIRANA
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Brian Gaudet

Person

Patents Grantslast 30 patents

Systems and methods for converting a P packet/cycle datapath to a Q...

Systems and methods for limiting the rates of data to/from a buffer

Systems and methods for routing data in a network device

Systems and methods for limiting the rates of data to/from a buffer

Systems and methods for converting a P packet/cycle datapath to a Q...

Systems and methods for routing data in a network device

Systems and methods for limiting the rates of data to/from a buffer

Systems and methods for converting a P packet/cycle datapath to a Q...

Scaleable gap insertion in a data link

Systems and methods for removing intrapacket gaps from streams of d...

Method and apparatus for equalizing propagation delay

High speed network switch bus clock

High-speed network switch bus

10/100 mb clock recovery architecture for switches, repeaters and m...

Adaptive differential ADC architecture

Ground bounce control using DLL to optimize output stage di/dt usin...

DLL calibrated phase multiplexer and interpolator

DLL calibrated switched current delay interpolator

Apparatus and method to adaptively equalize duty cycle distortion

Delay locked loop (DLL) based clock synthesis

1000 mb phase picker clock recovery architecture using interleaved...

Method and apparatus for adaptive equalization using feedback indic...

Scan flip-flop that holds state during shifting

Patents Applicationslast 30 patents

SYSTEMS AND METHODS FOR ROUTING DATA IN A NETWORK DEVICE

SYSTEMS AND METHODS FOR ROUTING DATA IN A NETWORK DEVICE