Brian J. Campbell

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit with separate supply voltage for memory that is...
- Patent number 10,490,265
- Issue date Nov 26, 2019
- Apple Inc.
- Brian J. Campbell
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit with separate supply voltage for memory that is...
- Patent number 10,482,952
- Issue date Nov 19, 2019
- Apple Inc.
- Brian J. Campbell
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit with separate supply voltage for memory that is...
- Patent number 9,672,901
- Issue date Jun 6, 2017
- Apple Inc.
- Brian J. Campbell
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit with separate supply voltage for memory that is...
- Patent number 9,343,139
- Issue date May 17, 2016
- Apple Inc.
- Brian J. Campbell
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit with separate supply voltage for memory that is...
- Patent number 9,129,708
- Issue date Sep 8, 2015
- Apple Inc.
- Brian J. Campbell
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit with separate supply voltage for memory that is...
- Patent number 8,848,463
- Issue date Sep 30, 2014
- Apple Inc.
- Brian J. Campbell
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit with separate supply voltage for memory that is...
- Patent number 8,625,368
- Issue date Jan 7, 2014
- Apple Inc.
- Brian J. Campbell
- G11 - INFORMATION STORAGE
Information Patent Grant
Performing stuck-at testing using multiple isolation circuits
- Patent number 8,553,488
- Issue date Oct 8, 2013
- Apple Inc.
- Brian J. Campbell
- G11 - INFORMATION STORAGE
Information Patent Grant
Level shifter with embedded logic and low minimum voltage
- Patent number 8,476,930
- Issue date Jul 2, 2013
- Apple Inc.
- Brian J. Campbell
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit with separate supply voltage for memory that is...
- Patent number 8,416,635
- Issue date Apr 9, 2013
- Apple Inc.
- Brian J. Campbell
- G11 - INFORMATION STORAGE
Information Patent Grant
Leakage and NBTI reduction technique for memory
- Patent number 8,395,954
- Issue date Mar 12, 2013
- Apple Inc.
- Brian J. Campbell
- G11 - INFORMATION STORAGE
Information Patent Grant
Clock gater with test features and low setup time
- Patent number 8,341,578
- Issue date Dec 25, 2012
- Apple Inc.
- Brian J. Campbell
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit with separate supply voltage for memory that is...
- Patent number 8,289,785
- Issue date Oct 16, 2012
- Apple Inc.
- Brian J. Campbell
- G11 - INFORMATION STORAGE
Information Patent Grant
Fast hit override
- Patent number 8,219,755
- Issue date Jul 10, 2012
- Apple Inc.
- Brian J. Campbell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Leakage and NBTI reduction technique for memory
- Patent number 8,203,898
- Issue date Jun 19, 2012
- Apple Inc.
- Brian J. Campbell
- G11 - INFORMATION STORAGE
Information Patent Grant
L1 flush mechanism to flush cache for power down and handle coheren...
- Patent number 8,171,326
- Issue date May 1, 2012
- Apple Inc.
- James B. Keller
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Cache optimizations using multiple threshold voltage transistors
- Patent number 8,102,728
- Issue date Jan 24, 2012
- Apple Inc.
- Brian J. Campbell
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit with separate supply voltage for memory that is...
- Patent number 8,098,534
- Issue date Jan 17, 2012
- Apple Inc.
- Brian J. Campbell
- G11 - INFORMATION STORAGE
Information Patent Grant
Fast hit override
- Patent number 8,015,356
- Issue date Sep 6, 2011
- Apple Inc.
- Brian J. Campbell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Leakage and NBTI reduction technique for memory
- Patent number 7,995,410
- Issue date Aug 9, 2011
- Apple Inc.
- Brian J. Campbell
- G11 - INFORMATION STORAGE
Information Patent Grant
Level shifter with embedded logic and low minimum voltage
- Patent number 7,994,820
- Issue date Aug 9, 2011
- Apple Inc.
- Brian J. Campbell
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low latency, power-down safe level shifter
- Patent number 7,915,920
- Issue date Mar 29, 2011
- Apple Inc.
- Brian J. Campbell
- G11 - INFORMATION STORAGE
Information Patent Grant
Level shifter with embedded logic and low minimum voltage
- Patent number 7,834,662
- Issue date Nov 16, 2010
- Apple Inc.
- Brian J. Campbell
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock gater with test features and low setup time
- Patent number 7,779,372
- Issue date Aug 17, 2010
- Apple Inc.
- Brian J. Campbell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit with separate supply voltage for memory that is...
- Patent number 7,760,559
- Issue date Jul 20, 2010
- Apple Inc.
- Brian J. Campbell
- G11 - INFORMATION STORAGE
Information Patent Grant
L1 cache flush when processor is entering low power mode
- Patent number 7,752,474
- Issue date Jul 6, 2010
- Apple Inc.
- James B. Keller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low latency, power-down safe level shifter
- Patent number 7,652,504
- Issue date Jan 26, 2010
- Apple Inc.
- Brian J. Campbell
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit with separate supply voltage for memory that is...
- Patent number 7,474,571
- Issue date Jan 6, 2009
- P.A. Semi, Inc.
- Brian J. Campbell
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit with separate supply voltage for memory that is...
- Patent number 7,355,905
- Issue date Apr 8, 2008
- P.A. Semi, Inc.
- Brian J. Campbell
- G11 - INFORMATION STORAGE
Information Patent Grant
Recovering bit lines in a memory array after stopped clock operation
- Patent number 7,218,562
- Issue date May 15, 2007
- P.A. Semi, Inc.
- Brian J. Campbell
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Integrated Circuit With Separate Supply Voltage For Memory That Is...
- Publication number 20180130524
- Publication date May 10, 2018
- Apple Inc.
- Brian J. Campbell
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated Circuit With Separate Supply Voltage For Memory That Is...
- Publication number 20170236578
- Publication date Aug 17, 2017
- Apple Inc.
- Brian J. Campbell
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated Circuit With Separate Supply Voltage For Memory That Is...
- Publication number 20160307621
- Publication date Oct 20, 2016
- Apple Inc.
- Brian J. Campbell
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated Circuit With Separate Supply Voltage For Memory That Is...
- Publication number 20150332754
- Publication date Nov 19, 2015
- Apple Inc.
- Brian J. Campbell
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated Circuit With Separate Supply Voltage For Memory That Is...
- Publication number 20140362639
- Publication date Dec 11, 2014
- Brian J. Campbell
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated Circuit With Separate Supply Voltage For Memory That Is...
- Publication number 20140092676
- Publication date Apr 3, 2014
- Apple Inc.
- Brian J. Campbell
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated Circuit With Separate Supply Voltage For Memory That Is...
- Publication number 20130182493
- Publication date Jul 18, 2013
- Apple Inc.
- Brian J. Campbell
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated Circuit with Separate Supply Voltage for Memory That is...
- Publication number 20130016575
- Publication date Jan 17, 2013
- Brian J. Campbell
- G11 - INFORMATION STORAGE
Information Patent Application
Performing Stuck-At Testing Using Multiple Isolation Circuits
- Publication number 20120314516
- Publication date Dec 13, 2012
- Brian J. Campbell
- G11 - INFORMATION STORAGE
Information Patent Application
Leakage and NBTI Reduction Technique for Memory
- Publication number 20120257469
- Publication date Oct 11, 2012
- Brian J. Campbell
- G11 - INFORMATION STORAGE
Information Patent Application
Fast Hit Override
- Publication number 20110289275
- Publication date Nov 24, 2011
- Brian J. Campbell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Level Shifter with Embedded Logic and Low Minimum Voltage
- Publication number 20110255351
- Publication date Oct 20, 2011
- Brian J. Campbell
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Leakage and NBTI Reduction Technique for Memory
- Publication number 20110255355
- Publication date Oct 20, 2011
- Brian J. Campbell
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated Circuit with Separate Supply Voltage for Memory That is...
- Publication number 20110235442
- Publication date Sep 29, 2011
- Brian J. Campbell
- G11 - INFORMATION STORAGE
Information Patent Application
Level Shifter with Embedded Logic and Low Minimum Voltage
- Publication number 20110032020
- Publication date Feb 10, 2011
- Brian J. Campbell
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Leakage and NBTI Reduction Technique for Memory
- Publication number 20100329062
- Publication date Dec 30, 2010
- Brian J. Campbell
- G11 - INFORMATION STORAGE
Information Patent Application
Clock Gater with Test Features and Low Setup Time
- Publication number 20100277219
- Publication date Nov 4, 2010
- Brian J. Campbell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cache Optimizations Using Multiple Threshold Voltage Transistors
- Publication number 20100254206
- Publication date Oct 7, 2010
- Brian J. Campbell
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated Circuit with Separate Supply Voltage for Memory That is...
- Publication number 20100238745
- Publication date Sep 23, 2010
- Brian J. Campbell
- G11 - INFORMATION STORAGE
Information Patent Application
Fast L1 Flush Mechanism
- Publication number 20100235670
- Publication date Sep 16, 2010
- James B. Keller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low Latency, Power-Down Safe Level Shifter
- Publication number 20100085079
- Publication date Apr 8, 2010
- Brian J. Campbell
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Level Shifter with Embedded Logic and Low Minimum Voltage
- Publication number 20090174458
- Publication date Jul 9, 2009
- Brian J. Campbell
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Integrated Circuit with Separate Supply Voltage for Memory That is...
- Publication number 20090080268
- Publication date Mar 26, 2009
- Brian J. Campbell
- G11 - INFORMATION STORAGE
Information Patent Application
Clock Gater with Test Features and Low Setup Time
- Publication number 20080180159
- Publication date Jul 31, 2008
- Brian J. Campbell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low Latency, Power-Down Safe Level Shifter
- Publication number 20080143417
- Publication date Jun 19, 2008
- Brian J. Campbell
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Integrated Circuit with Separate Supply Voltage for Memory That is...
- Publication number 20080137448
- Publication date Jun 12, 2008
- Brian J. Campbell
- G11 - INFORMATION STORAGE
Information Patent Application
Fast hit override
- Publication number 20070005891
- Publication date Jan 4, 2007
- P.A. Semi, Inc.
- Brian J. Campbell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated circuit with separate supply voltage for memory that is...
- Publication number 20070002636
- Publication date Jan 4, 2007
- P.A. Semi, Inc.
- Brian J. Campbell
- G11 - INFORMATION STORAGE
Information Patent Application
Recovering bit lines in a memory array after stopped clock operation
- Publication number 20070002650
- Publication date Jan 4, 2007
- P.A. Semi, Inc.
- Brian J. Campbell
- G11 - INFORMATION STORAGE
Information Patent Application
Scan interface
- Publication number 20050235185
- Publication date Oct 20, 2005
- Brian J. Campbell
- G01 - MEASURING TESTING

Brian J. Campbell

Person

Patents Grantslast 30 patents

Integrated circuit with separate supply voltage for memory that is...

Integrated circuit with separate supply voltage for memory that is...

Integrated circuit with separate supply voltage for memory that is...

Integrated circuit with separate supply voltage for memory that is...

Integrated circuit with separate supply voltage for memory that is...

Integrated circuit with separate supply voltage for memory that is...

Integrated circuit with separate supply voltage for memory that is...

Performing stuck-at testing using multiple isolation circuits

Level shifter with embedded logic and low minimum voltage

Integrated circuit with separate supply voltage for memory that is...

Leakage and NBTI reduction technique for memory

Clock gater with test features and low setup time

Integrated circuit with separate supply voltage for memory that is...

Fast hit override

Leakage and NBTI reduction technique for memory

L1 flush mechanism to flush cache for power down and handle coheren...

Cache optimizations using multiple threshold voltage transistors

Integrated circuit with separate supply voltage for memory that is...

Fast hit override

Leakage and NBTI reduction technique for memory

Level shifter with embedded logic and low minimum voltage

Low latency, power-down safe level shifter

Level shifter with embedded logic and low minimum voltage

Clock gater with test features and low setup time

Integrated circuit with separate supply voltage for memory that is...

L1 cache flush when processor is entering low power mode

Low latency, power-down safe level shifter

Integrated circuit with separate supply voltage for memory that is...

Integrated circuit with separate supply voltage for memory that is...

Recovering bit lines in a memory array after stopped clock operation

Patents Applicationslast 30 patents

Integrated Circuit With Separate Supply Voltage For Memory That Is...

Integrated Circuit With Separate Supply Voltage For Memory That Is...

Integrated Circuit With Separate Supply Voltage For Memory That Is...

Integrated Circuit With Separate Supply Voltage For Memory That Is...

Integrated Circuit With Separate Supply Voltage For Memory That Is...

Integrated Circuit With Separate Supply Voltage For Memory That Is...

Integrated Circuit With Separate Supply Voltage For Memory That Is...

Integrated Circuit with Separate Supply Voltage for Memory That is...

Performing Stuck-At Testing Using Multiple Isolation Circuits

Leakage and NBTI Reduction Technique for Memory

Fast Hit Override

Level Shifter with Embedded Logic and Low Minimum Voltage

Leakage and NBTI Reduction Technique for Memory

Integrated Circuit with Separate Supply Voltage for Memory That is...

Level Shifter with Embedded Logic and Low Minimum Voltage

Leakage and NBTI Reduction Technique for Memory

Clock Gater with Test Features and Low Setup Time

Cache Optimizations Using Multiple Threshold Voltage Transistors

Integrated Circuit with Separate Supply Voltage for Memory That is...

Fast L1 Flush Mechanism

Low Latency, Power-Down Safe Level Shifter

Level Shifter with Embedded Logic and Low Minimum Voltage

Integrated Circuit with Separate Supply Voltage for Memory That is...

Clock Gater with Test Features and Low Setup Time

Low Latency, Power-Down Safe Level Shifter

Integrated Circuit with Separate Supply Voltage for Memory That is...

Fast hit override

Integrated circuit with separate supply voltage for memory that is...

Recovering bit lines in a memory array after stopped clock operation

Scan interface