Brian P. Lilly

Person

San Francisco, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Request ordering in a cache
- Patent number 12,216,578
- Issue date Feb 4, 2025
- Apple Inc.
- Sandeep Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable cache coherency protocol
- Patent number 11,947,457
- Issue date Apr 2, 2024
- Apple Inc.
- James Vash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Variable hit latency cache
- Patent number 11,893,241
- Issue date Feb 6, 2024
- Apple Inc.
- Brian P. Lilly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable cache coherency protocol
- Patent number 11,868,258
- Issue date Jan 9, 2024
- Apple Inc.
- James Vash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coprocessor context priority
- Patent number 11,768,690
- Issue date Sep 26, 2023
- Apple Inc.
- Aditya Kesiraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Request ordering in a cache
- Patent number 11,741,009
- Issue date Aug 29, 2023
- Apple Inc.
- Sandeep Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable cache coherency protocol
- Patent number 11,544,193
- Issue date Jan 3, 2023
- Apple Inc.
- James Vash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coprocessor context priority
- Patent number 11,210,104
- Issue date Dec 28, 2021
- Apple Inc.
- Aditya Kesiraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel coherence and memory cache processing pipelines
- Patent number 11,138,111
- Issue date Oct 5, 2021
- Apple Inc.
- Muditha Kanchana
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for ensuring real-time snoop latency
- Patent number 10,795,818
- Issue date Oct 6, 2020
- Apple Inc.
- Harshavardhan Kaushikkar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Least recently used mechanism for cache line eviction from a cache...
- Patent number 9,563,575
- Issue date Feb 7, 2017
- Apple Inc.
- Brian P. Lilly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selective cache way-group power down
- Patent number 9,563,567
- Issue date Feb 7, 2017
- Apple Inc.
- Mahnaz P Sadoughi-Yarandi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for cache line eviction
- Patent number 9,529,730
- Issue date Dec 27, 2016
- Apple Inc.
- Mahnaz Sadoughi-Yarandi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
L2 cache retention mode
- Patent number 9,513,693
- Issue date Dec 6, 2016
- Apple Inc.
- Prashant Jain
- G11 - INFORMATION STORAGE
Information Patent Grant
Cache pre-fetch merge in pending request buffer
- Patent number 9,454,486
- Issue date Sep 27, 2016
- Apple Inc.
- Brian P. Lilly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selective victimization in a multi-level cache hierarchy
- Patent number 9,298,620
- Issue date Mar 29, 2016
- Apple Inc.
- Hari S. Kannan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for sharing private caches in a SoC
- Patent number 9,280,471
- Issue date Mar 8, 2016
- Apple Inc.
- Manu Gulati
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delaying cache data array updates
- Patent number 9,229,866
- Issue date Jan 5, 2016
- Apple Inc.
- Hari S. Kannan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Least recently used mechanism for cache line eviction from a cache...
- Patent number 9,176,879
- Issue date Nov 3, 2015
- Apple Inc.
- Brian P. Lilly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing fast to slow links in a bus fabric
- Patent number 9,170,768
- Issue date Oct 27, 2015
- Apple Inc.
- Jason M. Kassoff
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for determining tunable parameters to use in p...
- Patent number 9,152,210
- Issue date Oct 6, 2015
- Apple Inc.
- Erik P Machnicki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flush engine
- Patent number 9,128,857
- Issue date Sep 8, 2015
- Apple Inc.
- Brian P. Lilly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coordinated prefetching based on training in hierarchically cached...
- Patent number 9,098,418
- Issue date Aug 4, 2015
- Apple Inc.
- Hari S. Kannan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prefetching across page boundaries in hierarchically cached processors
- Patent number 9,047,198
- Issue date Jun 2, 2015
- Apple Inc.
- Hari S. Kannan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache policies for uncacheable memory requests
- Patent number 9,043,554
- Issue date May 26, 2015
- Apple Inc.
- Brian P. Lilly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
QoS management in the L2 cache
- Patent number 8,751,746
- Issue date Jun 10, 2014
- Apple Inc.
- Brian P. Lilly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Critical word forwarding with adaptive prediction
- Patent number 8,713,277
- Issue date Apr 29, 2014
- Apple Inc.
- Brian P. Lilly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Combining write buffer with dynamically adjustable flush metrics
- Patent number 8,566,528
- Issue date Oct 22, 2013
- Apple Inc.
- Peter J. Bannon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple critical word bypassing in a memory controller
- Patent number 8,458,406
- Issue date Jun 4, 2013
- Apple Inc.
- Sukalpa Biswas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Combining write buffer with dynamically adjustable flush metrics
- Patent number 8,352,685
- Issue date Jan 8, 2013
- Apple Inc.
- Peter J. Bannon
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Scalable Cache Coherency Protocol
- Publication number 20240273024
- Publication date Aug 15, 2024
- Apple Inc.
- James Vash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Request Ordering in a Cache
- Publication number 20230359557
- Publication date Nov 9, 2023
- Apple Inc.
- Sandeep Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scalable Cache Coherency Protocol
- Publication number 20230169003
- Publication date Jun 1, 2023
- Apple Inc.
- James Vash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scalable Cache Coherency Protocol
- Publication number 20230083397
- Publication date Mar 16, 2023
- Apple Inc.
- James Vash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scalable Cache Coherency Protocol
- Publication number 20220083472
- Publication date Mar 17, 2022
- Apple Inc.
- James Vash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Coprocessor Context Priority
- Publication number 20220083343
- Publication date Mar 17, 2022
- Aditya Kesiraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLEL COHERENCE AND MEMORY CACHE PROCESSING PIPELINES
- Publication number 20200081838
- Publication date Mar 12, 2020
- Apple Inc.
- Muditha Kanchana
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Least Recently Used Mechanism for Cache Line Eviction from a Cache...
- Publication number 20160055099
- Publication date Feb 25, 2016
- Apple Inc.
- Brian P. Lilly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS FOR CACHE LINE EVICTION
- Publication number 20150309944
- Publication date Oct 29, 2015
- Apple Inc.
- Mahnaz Sadoughi-Yarandi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELECTIVE CACHE WAY-GROUP POWER DOWN
- Publication number 20150309939
- Publication date Oct 29, 2015
- Apple Inc.
- Mahnaz Sadoughi-Yarandi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
L2 CACHE RETENTION MODE
- Publication number 20150277541
- Publication date Oct 1, 2015
- Apple Inc.
- Prashant Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELECTIVE VICTIMIZATION IN A MULTI-LEVEL CACHE HIERARCHY
- Publication number 20150149721
- Publication date May 28, 2015
- Apple Inc.
- Hari S. Kannan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DELAYING CACHE DATA ARRAY UPDATES
- Publication number 20150149722
- Publication date May 28, 2015
- Apple Inc.
- Hari S. Kannan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISM FOR SHARING PRIVATE CACHES IN A SOC
- Publication number 20150143044
- Publication date May 21, 2015
- Apple Inc.
- Manu Gulati
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Least Recently Used Mechanism for Cache Line Eviction from a Cache...
- Publication number 20150026404
- Publication date Jan 22, 2015
- Apple Inc.
- Brian P. Lilly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE PRE-FETCH MERGE IN PENDING REQUEST BUFFER
- Publication number 20150019824
- Publication date Jan 15, 2015
- Apple Inc.
- Brian P. Lilly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Determining Tunable Parameters to Use in P...
- Publication number 20140237276
- Publication date Aug 21, 2014
- Apple Inc.
- Erik P. Machnicki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Flush Engine
- Publication number 20140195737
- Publication date Jul 10, 2014
- Apple Inc.
- Brian P. Lilly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE POLICIES FOR UNCACHEABLE MEMORY REQUESTS
- Publication number 20140181403
- Publication date Jun 26, 2014
- Apple Inc.
- Brian P. Lilly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING FAST TO SLOW LINKS IN A BUS FABRIC
- Publication number 20140181571
- Publication date Jun 26, 2014
- Apple Inc.
- Jason M. Kassoff
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREFETCHING ACROSS PAGE BOUNDARIES IN HIERARCHICALLY CACHED PROCESSORS
- Publication number 20140149632
- Publication date May 29, 2014
- Apple Inc.
- Hari S. Kannan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock Gated Storage Array
- Publication number 20140119146
- Publication date May 1, 2014
- Apple Inc.
- Brian P. Lilly
- G11 - INFORMATION STORAGE
Information Patent Application
COORDINATED PREFETCHING IN HIERARCHICALLY CACHED PROCESSORS
- Publication number 20130254485
- Publication date Sep 26, 2013
- Hari S. Kannan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
QOS MANAGEMENT IN THE L2 CACHE
- Publication number 20130159633
- Publication date Jun 20, 2013
- Brian P. Lilly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Combining Write Buffer with Dynamically Adjustable Flush Metrics
- Publication number 20130103906
- Publication date Apr 25, 2013
- Apple Inc.
- Peter J. Bannon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiple Critical Word Bypassing in a Memory Controller
- Publication number 20120137078
- Publication date May 31, 2012
- Sukalpa Biswas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Combining Write Buffer with Dynamically Adjustable Flush Metrics
- Publication number 20120047332
- Publication date Feb 23, 2012
- Peter J. Bannon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Combined Single Error Correction/Device Kill Detection Code
- Publication number 20120017135
- Publication date Jan 19, 2012
- Brian P. Lilly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Critical Word Forwarding with Adaptive Prediction
- Publication number 20110296110
- Publication date Dec 1, 2011
- Brian P. Lilly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Latency Reduction for Cache Coherent Bus-Based Cache
- Publication number 20110197030
- Publication date Aug 11, 2011
- Brian P. Lilly
- G06 - COMPUTING CALCULATING COUNTING

Brian P. Lilly

Person

Patents Grantslast 30 patents

Request ordering in a cache

Scalable cache coherency protocol

Variable hit latency cache

Scalable cache coherency protocol

Coprocessor context priority

Request ordering in a cache

Scalable cache coherency protocol

Coprocessor context priority

Parallel coherence and memory cache processing pipelines

Method and apparatus for ensuring real-time snoop latency

Least recently used mechanism for cache line eviction from a cache...

Selective cache way-group power down

Methods for cache line eviction

L2 cache retention mode

Cache pre-fetch merge in pending request buffer

Selective victimization in a multi-level cache hierarchy

Mechanism for sharing private caches in a SoC

Delaying cache data array updates

Least recently used mechanism for cache line eviction from a cache...

Managing fast to slow links in a bus fabric

Method and apparatus for determining tunable parameters to use in p...

Flush engine

Coordinated prefetching based on training in hierarchically cached...

Prefetching across page boundaries in hierarchically cached processors

Cache policies for uncacheable memory requests

QoS management in the L2 cache

Critical word forwarding with adaptive prediction

Combining write buffer with dynamically adjustable flush metrics

Multiple critical word bypassing in a memory controller

Combining write buffer with dynamically adjustable flush metrics

Patents Applicationslast 30 patents

Scalable Cache Coherency Protocol

Request Ordering in a Cache

Scalable Cache Coherency Protocol

Scalable Cache Coherency Protocol

Scalable Cache Coherency Protocol

Coprocessor Context Priority

PARALLEL COHERENCE AND MEMORY CACHE PROCESSING PIPELINES

Least Recently Used Mechanism for Cache Line Eviction from a Cache...

METHODS FOR CACHE LINE EVICTION

SELECTIVE CACHE WAY-GROUP POWER DOWN

L2 CACHE RETENTION MODE

SELECTIVE VICTIMIZATION IN A MULTI-LEVEL CACHE HIERARCHY

DELAYING CACHE DATA ARRAY UPDATES

MECHANISM FOR SHARING PRIVATE CACHES IN A SOC

Least Recently Used Mechanism for Cache Line Eviction from a Cache...

CACHE PRE-FETCH MERGE IN PENDING REQUEST BUFFER

Method and Apparatus for Determining Tunable Parameters to Use in P...

Flush Engine

CACHE POLICIES FOR UNCACHEABLE MEMORY REQUESTS

MANAGING FAST TO SLOW LINKS IN A BUS FABRIC

PREFETCHING ACROSS PAGE BOUNDARIES IN HIERARCHICALLY CACHED PROCESSORS

Clock Gated Storage Array

COORDINATED PREFETCHING IN HIERARCHICALLY CACHED PROCESSORS

QOS MANAGEMENT IN THE L2 CACHE

Combining Write Buffer with Dynamically Adjustable Flush Metrics

Multiple Critical Word Bypassing in a Memory Controller

Combining Write Buffer with Dynamically Adjustable Flush Metrics

Combined Single Error Correction/Device Kill Detection Code

Critical Word Forwarding with Adaptive Prediction

Latency Reduction for Cache Coherent Bus-Based Cache