Brian S. Hausauer

Person

Spring, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for promoting memory read commands
- Patent number 6,631,437
- Issue date Oct 7, 2003
- Hewlett-Packard Development Company, L.P.
- Ryan Callison
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus-to-bus bridge in computer system, with fast burst memory range
- Patent number RE37980
- Issue date Feb 4, 2003
- Compaq Computer Corporation
- Bassam Elkhoury
- 710 - Electrical computers and digital data processing systems: input/output
Information Patent Grant
Lower address line prediction and substitution
- Patent number 6,438,627
- Issue date Aug 20, 2002
- Compaq Information Technologies Group, L.P.
- Brian S. Hausauer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus-to-bus bridge in computer system, with fast burst memory range
- Patent number 6,148,359
- Issue date Nov 14, 2000
- Compaq Computer Corporation
- Bassam Elkhoury
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Host bridge configured to mask a portion of peripheral devices coup...
- Patent number 6,141,708
- Issue date Oct 31, 2000
- Compaq Computer Corporation
- Siamak Tavallaei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delivering a request to write or read data before delivering an ear...
- Patent number 6,138,192
- Issue date Oct 24, 2000
- Compaq Computer Corporation
- Brian S. Hausauer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Lock protocol for PCI bus using an additional "superlock" signal on...
- Patent number 6,098,134
- Issue date Aug 1, 2000
- Compaq Computer Corp.
- Peter Michels
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delivering transactions between data buses in a computer system
- Patent number 6,070,209
- Issue date May 30, 2000
- Compaq Computer Corporations
- Brian S. Hausauer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer expansion slot and associated logic for automatically dete...
- Patent number 5,930,496
- Issue date Jul 27, 1999
- Compaq Computer Corporation
- John M. MacLaren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delayed transaction protocol for computer system bus
- Patent number 5,870,567
- Issue date Feb 9, 1999
- Compaq Computer Corporation
- Brian S. Hausauer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus-to-bus bridge in computer system, with fast burst memory range
- Patent number 5,835,741
- Issue date Nov 10, 1998
- Compaq Computer Corporation
- Bassam Elkhoury
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus error handler for PERR# and SERR# on dual PCI bus system
- Patent number 5,790,870
- Issue date Aug 4, 1998
- Compaq Computer Corporation
- Brian S. Hausauer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stopclock toggle system for powering two CPUs from a regulator only...
- Patent number 5,659,789
- Issue date Aug 19, 1997
- Compaq Computer Corporation
- Brian S. Hausauer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock doubler and smooth transfer circuit
- Patent number 5,590,316
- Issue date Dec 31, 1996
- Brian S. Hausauer
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Method and apparatus for promoting memory read commands
- Publication number 20040054841
- Publication date Mar 18, 2004
- Ryan Callison
- G06 - COMPUTING CALCULATING COUNTING

Brian S. Hausauer

Person

Patents Grantslast 30 patents

Method and apparatus for promoting memory read commands

Bus-to-bus bridge in computer system, with fast burst memory range

Lower address line prediction and substitution

Bus-to-bus bridge in computer system, with fast burst memory range

Host bridge configured to mask a portion of peripheral devices coup...

Delivering a request to write or read data before delivering an ear...

Lock protocol for PCI bus using an additional "superlock" signal on...

Delivering transactions between data buses in a computer system

Computer expansion slot and associated logic for automatically dete...

Delayed transaction protocol for computer system bus

Bus-to-bus bridge in computer system, with fast burst memory range

Bus error handler for PERR# and SERR# on dual PCI bus system

Stopclock toggle system for powering two CPUs from a regulator only...

Clock doubler and smooth transfer circuit

Patents Applicationslast 30 patents

Method and apparatus for promoting memory read commands