Brian S. Morris

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Artificial neural network training using flexible floating point te...
- Patent number 12,205,035
- Issue date Jan 21, 2025
- Intel Corporation
- Krishnakumar Nair
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared buffered memory routing
- Patent number 11,755,486
- Issue date Sep 12, 2023
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared buffered memory routing
- Patent number 11,113,196
- Issue date Sep 7, 2021
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sharing memory and I/O services between nodes
- Patent number 10,915,468
- Issue date Feb 9, 2021
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Securely exposing an accelerator to privileged system components
- Patent number 10,762,244
- Issue date Sep 1, 2020
- Intel Corporation
- Joshua Fender
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Supporting configurable security levels for memory address ranges
- Patent number 10,671,740
- Issue date Jun 2, 2020
- Intel Corporation
- Binata Bhattacharyya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for partial cache line sparing
- Patent number 10,579,464
- Issue date Mar 3, 2020
- Intel Corporation
- Debaleena Das
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error handling in transactional buffered memory
- Patent number 10,360,096
- Issue date Jul 23, 2019
- Intel Corporation
- Brian S. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Early identification in transactional buffered memory
- Patent number 10,198,379
- Issue date Feb 5, 2019
- Intel Corporation
- Brian S. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Supporting multiple memory types in a memory slot
- Patent number 10,163,508
- Issue date Dec 25, 2018
- Intel Corporation
- Woojong Han
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for probabilistic dynamic random access memory row repair
- Patent number 10,102,886
- Issue date Oct 16, 2018
- Intel Corporation
- John H. Crawford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Packed write completions
- Patent number 10,061,719
- Issue date Aug 28, 2018
- Intel Corporation
- Brian S. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for a non-power-of-2 size cache in a first lev...
- Patent number 10,042,562
- Issue date Aug 7, 2018
- Intel Corporation
- Vedaraman Geetha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Protect non-memory encryption engine (non-mee) metadata in trusted...
- Patent number 10,031,861
- Issue date Jul 24, 2018
- Intel Corporation
- Siddhartha Chhabra
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Implementation of reserved cache slots in computing system having i...
- Patent number 10,007,606
- Issue date Jun 26, 2018
- Intel Corporation
- Vedaraman Geetha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Supporting configurable security levels for memory address ranges
- Patent number 9,959,418
- Issue date May 1, 2018
- Intel Corporation
- Binata Bhattacharyya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mapping a physical address differently to different memory devices...
- Patent number 9,934,143
- Issue date Apr 3, 2018
- Intel Corporation
- Kuljit S. Bains
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for partial cache line sparing
- Patent number 9,910,728
- Issue date Mar 6, 2018
- Intel Corporation
- Debaleena Das
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for determining victim row addresses in a volatile memory
- Patent number 9,824,754
- Issue date Nov 21, 2017
- Intel Corporation
- Sreenivas Mandava
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for a non-power-of-2 size cache in a first lev...
- Patent number 9,747,041
- Issue date Aug 29, 2017
- Intel Corporation
- Vedaraman Geetha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Early identification in transactional buffered memory
- Patent number 9,740,646
- Issue date Aug 22, 2017
- Intel Corporation
- Brian S. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared buffered memory routing
- Patent number 9,720,838
- Issue date Aug 1, 2017
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Speculative reads in buffered memory
- Patent number 9,658,963
- Issue date May 23, 2017
- Intel Corporation
- Brian S. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error handling in transactional buffered memory
- Patent number 9,632,862
- Issue date Apr 25, 2017
- Intel Corporation
- Brian S. Morris
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for reverse memory sparing
- Patent number 9,613,722
- Issue date Apr 4, 2017
- Intel Corporation
- George H. Huang
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for probabilistic dynamic random access memory row repair
- Patent number 9,449,671
- Issue date Sep 20, 2016
- Intel Corporation
- John H. Crawford
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for determining victim row addresses in a volatile memory
- Patent number 9,269,436
- Issue date Feb 23, 2016
- Intel Corporation
- Sreenivas Mandava
- G11 - INFORMATION STORAGE
Information Patent Grant
Virtual device sparing
- Patent number 9,201,748
- Issue date Dec 1, 2015
- Intel Corporation
- Brian S. Morris
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SHARING MEMORY AND I/O SERVICES BETWEEN NODES
- Publication number 20240160585
- Publication date May 16, 2024
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARTIFICIAL NEURAL NETWORK TRAINING USING FLEXIBLE FLOATING POINT TE...
- Publication number 20240028905
- Publication date Jan 25, 2024
- Intel Corporation
- Krishnakumar Nair
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARED BUFFERED MEMORY ROUTING
- Publication number 20240012759
- Publication date Jan 11, 2024
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARING MEMORY AND I/O SERVICES BETWEEN NODES
- Publication number 20220012189
- Publication date Jan 13, 2022
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARING MEMORY AND I/O SERVICES BETWEEN NODES
- Publication number 20210303482
- Publication date Sep 30, 2021
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS TO ACCELERATE MATRIX MULTIPLICATION
- Publication number 20210263993
- Publication date Aug 26, 2021
- Maciej URBANSKI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARED BUFFERED MEMORY ROUTING
- Publication number 20210240623
- Publication date Aug 5, 2021
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SECURELY EXPOSING AN ACCELERATOR TO PRIVILEGED SYSTEM COMPONENTS
- Publication number 20200327256
- Publication date Oct 15, 2020
- Intel Corporation
- JOSHUA FENDER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARED BUFFERED MEMORY ROUTING
- Publication number 20190108124
- Publication date Apr 11, 2019
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARTIFICIAL NEURAL NETWORK TRAINING USING FLEXIBLE FLOATING POINT TE...
- Publication number 20190042944
- Publication date Feb 7, 2019
- Intel Corporation
- Krishnakumar Nair
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SECURELY EXPOSING AN ACCELERATOR TO PRIVILEGED SYSTEM COMPONENTS
- Publication number 20190042801
- Publication date Feb 7, 2019
- JOSHUA FENDER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUPPORTING CONFIGURABLE SECURITY LEVELS FOR MEMORY ADDRESS RANGES
- Publication number 20180365438
- Publication date Dec 20, 2018
- Intel Corporation
- Binata Bhattacharyya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR PARTIAL CACHE LINE SPARING
- Publication number 20180196709
- Publication date Jul 12, 2018
- Intel Corporation
- Debaleena Das
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARED BUFFERED MEMORY ROUTING
- Publication number 20180067855
- Publication date Mar 8, 2018
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EARLY IDENTIFICATION IN TRANSACTIONAL BUFFERED MEMORY
- Publication number 20180060259
- Publication date Mar 1, 2018
- Intel Corporation
- Brian S. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPECULATIVE READS IN BUFFERED MEMORY
- Publication number 20180018267
- Publication date Jan 18, 2018
- Intel Corporation
- Brian S. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR A NON-POWER-OF-2 SIZE CACHE IN A FIRST LEV...
- Publication number 20180004433
- Publication date Jan 4, 2018
- Intel Corporation
- Vedaraman Geetha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ERROR HANDLING IN TRANSACTIONAL BUFFERED MEMORY
- Publication number 20170322841
- Publication date Nov 9, 2017
- Intel Corporation
- Brian S. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Implementation of Reserved Cache Slots in Computing System Having I...
- Publication number 20170286298
- Publication date Oct 5, 2017
- Intel Corporation
- Vedaraman GEETHA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUPPORTING MULTIPLE MEMORY TYPES IN A MEMORY SLOT
- Publication number 20170249991
- Publication date Aug 31, 2017
- Intel Corporation
- Woojong Han
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS AND METHOD FOR A NON-POWER-OF-2 SIZE CACHE IN A FIRST LEV...
- Publication number 20170185315
- Publication date Jun 29, 2017
- Intel Corporation
- Vedaraman Geetha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for partial cache line sparing
- Publication number 20170185473
- Publication date Jun 29, 2017
- Intel Corporation
- Debaleena Das
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techniques for Probabilistic Dynamic Random Access Memory Row Repair
- Publication number 20170103795
- Publication date Apr 13, 2017
- Intel Corporation
- John H. Crawford
- G11 - INFORMATION STORAGE
Information Patent Application
PROTECT NON-MEMORY ENCRYPTION ENGINE (NON-MEE) METADATA IN TRUSTED...
- Publication number 20170091119
- Publication date Mar 30, 2017
- Intel Corporation
- Siddhartha Chhabra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUPPORTING CONFIGURABLE SECURITY LEVELS FOR MEMORY ADDRESS RANGES
- Publication number 20170024573
- Publication date Jan 26, 2017
- Binata Bhattacharyya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARING MEMORY AND I/O SERVICES BETWEEN NODES
- Publication number 20170004098
- Publication date Jan 5, 2017
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARED BUFFERED MEMORY ROUTING
- Publication number 20160283375
- Publication date Sep 29, 2016
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techniques for Determining Victim Row Addresses in a Volatile Memory
- Publication number 20160224262
- Publication date Aug 4, 2016
- Intel Corporation
- SREENIVAS MANDAVA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PACKED WRITE COMPLETIONS
- Publication number 20160188500
- Publication date Jun 30, 2016
- Intel Corporation
- Brian S. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPECULATIVE READS IN BUFFERED MEMORY
- Publication number 20160179679
- Publication date Jun 23, 2016
- Intel Corporation
- Brian S. Morris
- G06 - COMPUTING CALCULATING COUNTING

Brian S. Morris

Person

Patents Grantslast 30 patents

Artificial neural network training using flexible floating point te...

Shared buffered memory routing

Shared buffered memory routing

Sharing memory and I/O services between nodes

Securely exposing an accelerator to privileged system components

Supporting configurable security levels for memory address ranges

Method and apparatus for partial cache line sparing

Error handling in transactional buffered memory

Early identification in transactional buffered memory

Supporting multiple memory types in a memory slot

Techniques for probabilistic dynamic random access memory row repair

Packed write completions

Apparatus and method for a non-power-of-2 size cache in a first lev...

Protect non-memory encryption engine (non-mee) metadata in trusted...

Implementation of reserved cache slots in computing system having i...

Supporting configurable security levels for memory address ranges

Mapping a physical address differently to different memory devices...

Method and apparatus for partial cache line sparing

Techniques for determining victim row addresses in a volatile memory

Apparatus and method for a non-power-of-2 size cache in a first lev...

Early identification in transactional buffered memory

Shared buffered memory routing

Speculative reads in buffered memory

Error handling in transactional buffered memory

Method and apparatus for reverse memory sparing

Techniques for probabilistic dynamic random access memory row repair

Techniques for determining victim row addresses in a volatile memory

Virtual device sparing

Patents Applicationslast 30 patents

SHARING MEMORY AND I/O SERVICES BETWEEN NODES

ARTIFICIAL NEURAL NETWORK TRAINING USING FLEXIBLE FLOATING POINT TE...

SHARED BUFFERED MEMORY ROUTING

SHARING MEMORY AND I/O SERVICES BETWEEN NODES

SHARING MEMORY AND I/O SERVICES BETWEEN NODES

APPARATUSES AND METHODS TO ACCELERATE MATRIX MULTIPLICATION

SHARED BUFFERED MEMORY ROUTING

SECURELY EXPOSING AN ACCELERATOR TO PRIVILEGED SYSTEM COMPONENTS

SHARED BUFFERED MEMORY ROUTING

ARTIFICIAL NEURAL NETWORK TRAINING USING FLEXIBLE FLOATING POINT TE...

SECURELY EXPOSING AN ACCELERATOR TO PRIVILEGED SYSTEM COMPONENTS

SUPPORTING CONFIGURABLE SECURITY LEVELS FOR MEMORY ADDRESS RANGES

METHOD AND APPARATUS FOR PARTIAL CACHE LINE SPARING

SHARED BUFFERED MEMORY ROUTING

EARLY IDENTIFICATION IN TRANSACTIONAL BUFFERED MEMORY

SPECULATIVE READS IN BUFFERED MEMORY

APPARATUS AND METHOD FOR A NON-POWER-OF-2 SIZE CACHE IN A FIRST LEV...

ERROR HANDLING IN TRANSACTIONAL BUFFERED MEMORY

Implementation of Reserved Cache Slots in Computing System Having I...

SUPPORTING MULTIPLE MEMORY TYPES IN A MEMORY SLOT

APPARATUS AND METHOD FOR A NON-POWER-OF-2 SIZE CACHE IN A FIRST LEV...

Method and apparatus for partial cache line sparing

Techniques for Probabilistic Dynamic Random Access Memory Row Repair

PROTECT NON-MEMORY ENCRYPTION ENGINE (NON-MEE) METADATA IN TRUSTED...

SUPPORTING CONFIGURABLE SECURITY LEVELS FOR MEMORY ADDRESS RANGES

SHARING MEMORY AND I/O SERVICES BETWEEN NODES

SHARED BUFFERED MEMORY ROUTING

Techniques for Determining Victim Row Addresses in a Volatile Memory

PACKED WRITE COMPLETIONS

SPECULATIVE READS IN BUFFERED MEMORY