Brian S. Schieck

Person

Hayward, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
IC package design and methodology to compensate for die-substrate C...
- Patent number 11,495,568
- Issue date Nov 8, 2022
- NVIDIA Corporation
- Jayprakash Chipalkatti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
IC package design and methodology to compensate for die-substrate C...
- Patent number 10,943,882
- Issue date Mar 9, 2021
- NVIDIA Corporation
- Jayprakash Chipalkatti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package structure
- Patent number 10,032,692
- Issue date Jul 24, 2018
- NVIDIA Corporation
- Shantanu Kalchuri
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low-impedance power delivery for a packaged die
- Patent number 9,831,225
- Issue date Nov 28, 2017
- NVIDIA Corporation
- Gurpreet Shinh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low-impedance power delivery for a packaged die
- Patent number 9,190,396
- Issue date Nov 17, 2015
- NVIDIA Corporation
- Gurpreet Shinh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a flip chip semiconductor die with internal s...
- Patent number 8,951,814
- Issue date Feb 10, 2015
- NVIDIA Corporation
- Brian S. Schieck
- G01 - MEASURING TESTING
Information Patent Grant
Flip chip semiconductor die internal signal access system and method
- Patent number 8,357,931
- Issue date Jan 22, 2013
- NVIDIA Corporation
- Brian S. Schieck
- G01 - MEASURING TESTING
Information Patent Grant
Flip chip semiconductor die internal signal access system and method
- Patent number 7,842,948
- Issue date Nov 30, 2010
- NVIDIA Corporation
- Brian S. Schieck
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
IC PACKAGE DESIGN AND METHODOLOGY TO COMPENSATE FOR DIE-SUBSTRATE C...
- Publication number 20210151403
- Publication date May 20, 2021
- NVIDIA Corporation
- Jayprakash Chipalkatti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IC PACKAGE DESIGN AND METHODOLOGY TO COMPENSATE FOR DIE-SUBSTRATE C...
- Publication number 20210066227
- Publication date Mar 4, 2021
- NVIDIA Corporation
- Jayprakash Chipalkatti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW-IMPEDANCE POWER DELIVERY FOR A PACKAGED DIE
- Publication number 20160148915
- Publication date May 26, 2016
- NVIDIA Corporation
- Gurpreet SHINH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE STRUCTURE
- Publication number 20140264816
- Publication date Sep 18, 2014
- NVIDIA Corporation
- Shantanu Kalchuri
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW-IMPEDANCE POWER DELIVERY FOR A PACKAGED DIE
- Publication number 20140042637
- Publication date Feb 13, 2014
- Gurpreet SHINH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLIP CHIP SEMICONDUCTOR DIE INTERNAL SIGNAL ACCESS SYSTEM AND METHOD
- Publication number 20130221354
- Publication date Aug 29, 2013
- NVIDIA Corporation
- Brian S. Schieck
- G01 - MEASURING TESTING
Information Patent Application
Flip chip semiconductor die internal signal access system and method
- Publication number 20080128695
- Publication date Jun 5, 2008
- Brian S. Schieck
- G01 - MEASURING TESTING
Information Patent Application
Flip chip semiconductor die internal signal access system and method
- Publication number 20050191770
- Publication date Sep 1, 2005
- Brian S. Schieck
- G01 - MEASURING TESTING

Brian S. Schieck

Person

Patents Grantslast 30 patents

IC package design and methodology to compensate for die-substrate C...

IC package design and methodology to compensate for die-substrate C...

Semiconductor package structure

Low-impedance power delivery for a packaged die

Low-impedance power delivery for a packaged die

Method of fabricating a flip chip semiconductor die with internal s...

Flip chip semiconductor die internal signal access system and method

Flip chip semiconductor die internal signal access system and method

Patents Applicationslast 30 patents

IC PACKAGE DESIGN AND METHODOLOGY TO COMPENSATE FOR DIE-SUBSTRATE C...

IC PACKAGE DESIGN AND METHODOLOGY TO COMPENSATE FOR DIE-SUBSTRATE C...

LOW-IMPEDANCE POWER DELIVERY FOR A PACKAGED DIE

SEMICONDUCTOR PACKAGE STRUCTURE

LOW-IMPEDANCE POWER DELIVERY FOR A PACKAGED DIE

FLIP CHIP SEMICONDUCTOR DIE INTERNAL SIGNAL ACCESS SYSTEM AND METHOD

Flip chip semiconductor die internal signal access system and method

Flip chip semiconductor die internal signal access system and method