Brian W. Condie

Person

Mesa, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor device with a buffer region with tightly-packed fille...
- Patent number 7,701,074
- Issue date Apr 20, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Brian W. Condie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and apparatus for a reduced inductance wirebond array
- Patent number 7,683,480
- Issue date Mar 23, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Mario M. Bokatius
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure and method of assembly
- Patent number 7,446,411
- Issue date Nov 4, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Brian W. Condie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with reduced package cross-talk and loss
- Patent number 7,435,625
- Issue date Oct 14, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Brian W. Condie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Plastic packaged device with die interface layer
- Patent number 7,432,133
- Issue date Oct 7, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Brian W. Condie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure and method of manufacture
- Patent number 7,429,790
- Issue date Sep 30, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Brian W. Condie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chemical die singulation technique
- Patent number 7,332,414
- Issue date Feb 19, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Brian W. Condie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low stress semiconductor die attach
- Patent number 7,042,103
- Issue date May 9, 2006
- Motorola, Inc.
- Brian W. Condie
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR DEVICE WITH A BUFFER REGION WITH TIGHTLY-PACKED FILLE...
- Publication number 20090001614
- Publication date Jan 1, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Brian W. Condie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods and apparatus for a reduced inductance wirebond array
- Publication number 20070235855
- Publication date Oct 11, 2007
- Mario M. Bokatius
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Plastic packaged device with die interface layer
- Publication number 20070090543
- Publication date Apr 26, 2007
- Brian W. Condie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device with improved encapsulation
- Publication number 20070090545
- Publication date Apr 26, 2007
- Brian W. Condie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor structure and method of manufacture
- Publication number 20070090514
- Publication date Apr 26, 2007
- Freescale Semiconductor, Inc.
- Brian W. Condie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor structure and method of assembly
- Publication number 20070090515
- Publication date Apr 26, 2007
- Freescale Semiconductor, Inc.
- Brian W. Condie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device with reduced package cross-talk and loss
- Publication number 20070090542
- Publication date Apr 26, 2007
- Brian W. Condie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Chemical die singulation technique
- Publication number 20060292827
- Publication date Dec 28, 2006
- Brian W. Condie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Low stress semiconductor die attach
- Publication number 20040124543
- Publication date Jul 1, 2004
- MOTOROLA INC.
- Brian W. Condie
- H01 - BASIC ELECTRIC ELEMENTS

Brian W. Condie

Person

Patents Grantslast 30 patents

Semiconductor device with a buffer region with tightly-packed fille...

Methods and apparatus for a reduced inductance wirebond array

Semiconductor structure and method of assembly

Semiconductor device with reduced package cross-talk and loss

Plastic packaged device with die interface layer

Semiconductor structure and method of manufacture

Chemical die singulation technique

Low stress semiconductor die attach

Patents Applicationslast 30 patents

SEMICONDUCTOR DEVICE WITH A BUFFER REGION WITH TIGHTLY-PACKED FILLE...

Methods and apparatus for a reduced inductance wirebond array

Plastic packaged device with die interface layer

Semiconductor device with improved encapsulation

Semiconductor structure and method of manufacture

Semiconductor structure and method of assembly

Semiconductor device with reduced package cross-talk and loss

Chemical die singulation technique

Low stress semiconductor die attach