Bruce Beattie

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Cavity spacer for nanowire transistors
- Patent number 11,929,396
- Issue date Mar 12, 2024
- Intel Corporation
- William Hsu
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Dielectric isolation layer between a nanowire transistor and a subs...
- Patent number 11,901,458
- Issue date Feb 13, 2024
- Intel Corporation
- Bruce E. Beattie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate-all-around integrated circuit structures fabricated using alte...
- Patent number 11,894,368
- Issue date Feb 6, 2024
- Intel Corporation
- Sudipto Naskar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-planar integrated circuit structures having mitigated source or...
- Patent number 11,869,891
- Issue date Jan 9, 2024
- Intel Corporation
- Jun Sung Kang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nanowire transistor structure and method of shaping
- Patent number 11,869,973
- Issue date Jan 9, 2024
- Intel Corporation
- Erica J. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned nanowire
- Patent number 11,715,787
- Issue date Aug 1, 2023
- Intel Corporation
- Mark Armstrong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dielectric isolation layer between a nanowire transistor and a subs...
- Patent number 11,404,578
- Issue date Aug 2, 2022
- Intel Corporation
- Bruce E. Beattie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Cavity spacer for nanowire transistors
- Patent number 11,342,411
- Issue date May 24, 2022
- Intel Corporation
- William Hsu
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Gate-all-around integrated circuit structures having self-aligned s...
- Patent number 11,276,691
- Issue date Mar 15, 2022
- Intel Corporation
- Biswajeet Guha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned nanowire
- Patent number 11,205,715
- Issue date Dec 21, 2021
- Intel Corporation
- Mark Armstrong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistors with channel and sub-channel regions with distinct comp...
- Patent number 11,069,795
- Issue date Jul 20, 2021
- Intel Corporation
- Karthik Jambunathan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional germanium-based semiconductor devices formed on g...
- Patent number 9,472,399
- Issue date Oct 18, 2016
- Intel Corporation
- Annalisa Cappellani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional germanium-based semiconductor devices formed on g...
- Patent number 9,041,106
- Issue date May 26, 2015
- Intel Corporation
- Annalisa Cappellani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit with multiple gate dielectric structures
- Patent number 6,597,046
- Issue date Jul 22, 2003
- Intel Corporation
- Robert S. Chau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Post etch clean sequence for making a semiconductor device
- Patent number 6,465,358
- Issue date Oct 15, 2002
- Intel Corporation
- Michael S. Nashner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming gate oxide having dual thickness by oxidation pro...
- Patent number 6,124,171
- Issue date Sep 26, 2000
- Intel Corporation
- Reza Arghavani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit with multiple gate dielectric structures
- Patent number 6,087,236
- Issue date Jul 11, 2000
- Intel Corporation
- Robert S. Chau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Cantilever and cold zone assembly for loading and unloading an oven
- Patent number 4,909,185
- Issue date Mar 20, 1990
- Weiss Scientific Glass Blowing Co.
- Robert E. Aldridge
- C30 - CRYSTAL GROWTH

Patents Applicationslast 30 patents

Information Patent Application
Cavity Spacer for Nanowire Transistors
- Publication number 20240347595
- Publication date Oct 17, 2024
- Intel Corporation
- William Hsu
- B82 - NANO-TECHNOLOGY
Information Patent Application
DIELECTRIC ISOLATION LAYER BETWEEN A NANOWIRE TRANSISTOR AND A SUBS...
- Publication number 20240145598
- Publication date May 2, 2024
- Intel Corporation
- Bruce E. Beattie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES FABRICATED USING ALTE...
- Publication number 20240120335
- Publication date Apr 11, 2024
- Intel Corporation
- Sudipto NASKAR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NON-PLANAR INTEGRATED CIRCUIT STRUCTURES HAVING MITIGATED SOURCE OR...
- Publication number 20240096896
- Publication date Mar 21, 2024
- Intel Corporation
- Jun Sung KANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NANOWIRE TRANSISTOR STRUCTURE AND METHOD OF SHAPING
- Publication number 20240088296
- Publication date Mar 14, 2024
- Intel Corporation
- Erica J. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIELECTRIC ISOLATION LAYER BETWEEN A NANOWIRE TRANSISTOR AND A SUBS...
- Publication number 20220336668
- Publication date Oct 20, 2022
- Intel Corporation
- Bruce E. Beattie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CAVITY SPACER FOR NANOWIRE TRANSISTORS
- Publication number 20220246721
- Publication date Aug 4, 2022
- Intel Corporation
- William Hsu
- B82 - NANO-TECHNOLOGY
Information Patent Application
SELF-ALIGNED NANOWIRE
- Publication number 20220052178
- Publication date Feb 17, 2022
- Intel Corporation
- Mark Armstrong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES FABRICATED USING ALTE...
- Publication number 20210202479
- Publication date Jul 1, 2021
- Intel Corporation
- Sudipto NASKAR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTORS WITH CHANNEL AND SUB-CHANNEL REGIONS WITH DISTINCT COMP...
- Publication number 20200411513
- Publication date Dec 31, 2020
- Intel Corporation
- Karthik Jambunathan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED NANOWIRE
- Publication number 20200152767
- Publication date May 14, 2020
- Intel Corporation
- Mark Armstrong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NON-PLANAR INTEGRATED CIRCUIT STRUCTURES HAVING MITIGATED SOURCE OR...
- Publication number 20200105757
- Publication date Apr 2, 2020
- Intel Corporation
- Jun Sung KANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING SELF-ALIGNED S...
- Publication number 20200091145
- Publication date Mar 19, 2020
- Intel Corporation
- Biswajeet GUHA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CAVITY SPACER FOR NANOWIRE TRANSISTORS
- Publication number 20200006478
- Publication date Jan 2, 2020
- Intel Corporation
- William Hsu
- B82 - NANO-TECHNOLOGY
Information Patent Application
NANOWIRE TRANSISTOR STRUCTURE AND METHOD OF SHAPING
- Publication number 20190393350
- Publication date Dec 26, 2019
- Intel Corporation
- Erica J. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIELECTRIC ISOLATION LAYER BETWEEN A NANOWIRE TRANSISTOR AND A SUBS...
- Publication number 20190393351
- Publication date Dec 26, 2019
- Intel Corporation
- Bruce E. Beattie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL GERMANIUM-BASED SEMICONDUCTOR DEVICES FORMED ON G...
- Publication number 20170025499
- Publication date Jan 26, 2017
- Annalisa Cappellani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL GERMANIUM-BASED SEMICONDUCTOR DEVICES FORMED ON G...
- Publication number 20150255280
- Publication date Sep 10, 2015
- Annalisa Cappellani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL GERMANIUM-BASED SEMICONDUCTOR DEVICES FORMED ON G...
- Publication number 20140084370
- Publication date Mar 27, 2014
- Annalisa Cappellani
- B82 - NANO-TECHNOLOGY
Information Patent Application
Methods of corrosion prevention and cleaning of copper structures
- Publication number 20080152812
- Publication date Jun 26, 2008
- Ming Fang
- C11 - ANIMAL AND VEGETABLE OILS, FATS, FATTY SUBSTANCES AND WAXES FATTY ACIDS...
Information Patent Application
Selective etching silicon nitride
- Publication number 20050159011
- Publication date Jul 21, 2005
- Vani K. Thirumala
- H01 - BASIC ELECTRIC ELEMENTS

Bruce Beattie

Person

Patents Grantslast 30 patents

Cavity spacer for nanowire transistors

Dielectric isolation layer between a nanowire transistor and a subs...

Gate-all-around integrated circuit structures fabricated using alte...

Non-planar integrated circuit structures having mitigated source or...

Nanowire transistor structure and method of shaping

Self-aligned nanowire

Dielectric isolation layer between a nanowire transistor and a subs...

Cavity spacer for nanowire transistors

Gate-all-around integrated circuit structures having self-aligned s...

Self-aligned nanowire

Transistors with channel and sub-channel regions with distinct comp...

Three-dimensional germanium-based semiconductor devices formed on g...

Three-dimensional germanium-based semiconductor devices formed on g...

Integrated circuit with multiple gate dielectric structures

Post etch clean sequence for making a semiconductor device

Method of forming gate oxide having dual thickness by oxidation pro...

Integrated circuit with multiple gate dielectric structures

Cantilever and cold zone assembly for loading and unloading an oven

Patents Applicationslast 30 patents

Cavity Spacer for Nanowire Transistors

DIELECTRIC ISOLATION LAYER BETWEEN A NANOWIRE TRANSISTOR AND A SUBS...

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES FABRICATED USING ALTE...

NON-PLANAR INTEGRATED CIRCUIT STRUCTURES HAVING MITIGATED SOURCE OR...

NANOWIRE TRANSISTOR STRUCTURE AND METHOD OF SHAPING

DIELECTRIC ISOLATION LAYER BETWEEN A NANOWIRE TRANSISTOR AND A SUBS...

CAVITY SPACER FOR NANOWIRE TRANSISTORS

SELF-ALIGNED NANOWIRE

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES FABRICATED USING ALTE...

TRANSISTORS WITH CHANNEL AND SUB-CHANNEL REGIONS WITH DISTINCT COMP...

SELF-ALIGNED NANOWIRE

NON-PLANAR INTEGRATED CIRCUIT STRUCTURES HAVING MITIGATED SOURCE OR...

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING SELF-ALIGNED S...

CAVITY SPACER FOR NANOWIRE TRANSISTORS

NANOWIRE TRANSISTOR STRUCTURE AND METHOD OF SHAPING

DIELECTRIC ISOLATION LAYER BETWEEN A NANOWIRE TRANSISTOR AND A SUBS...

THREE-DIMENSIONAL GERMANIUM-BASED SEMICONDUCTOR DEVICES FORMED ON G...

THREE-DIMENSIONAL GERMANIUM-BASED SEMICONDUCTOR DEVICES FORMED ON G...

THREE-DIMENSIONAL GERMANIUM-BASED SEMICONDUCTOR DEVICES FORMED ON G...

Methods of corrosion prevention and cleaning of copper structures

Selective etching silicon nitride