Bruce MILLAR

Person

Stittsville, CA

People

Patents Grantslast 30 patents

Information Patent Grant
Dynamic impedance control for input/output buffers
- Patent number 10,985,757
- Issue date Apr 20, 2021
- Conversant Intellectual Property Management Inc.
- Bruce Millar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamic impedance control for input/output buffers
- Patent number 10,608,634
- Issue date Mar 31, 2020
- Conversant Intellectual Property Management Inc.
- Bruce Millar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamic impedance control for input/output buffers
- Patent number 9,300,291
- Issue date Mar 29, 2016
- Conversant Intellectual Property Management Inc.
- Bruce Millar
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic impedance control for input/output buffers
- Patent number 8,847,623
- Issue date Sep 30, 2014
- Conversant Intellectual Property Management Inc.
- Bruce Millar
- G11 - INFORMATION STORAGE
Information Patent Grant
High bandwidth memory interface
- Patent number 8,654,573
- Issue date Feb 18, 2014
- MOSAID Technologies Incorporated
- Peter B. Gillingham
- G11 - INFORMATION STORAGE
Information Patent Grant
Voltage down converter for high speed memory
- Patent number 8,611,171
- Issue date Dec 17, 2013
- MOSAID Technologies Incorporated
- Hong Beom Pyeon
- G11 - INFORMATION STORAGE
Information Patent Grant
High bandwidth memory interface
- Patent number 8,266,372
- Issue date Sep 11, 2012
- MOSAID Technologies Incorporated
- Peter Gillingham
- G11 - INFORMATION STORAGE
Information Patent Grant
High bandwidth memory interface
- Patent number 8,250,297
- Issue date Aug 21, 2012
- MOSAID Technologies Incorporated
- Peter Gillingham
- G11 - INFORMATION STORAGE
Information Patent Grant
Voltage down converter for high speed memory
- Patent number 8,164,968
- Issue date Apr 24, 2012
- MOSAID Technologies Incorporated
- Hong Beom Pyeon
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic impedance control for input/output buffers
- Patent number 8,035,413
- Issue date Oct 11, 2011
- Mosaid Technologies Incorporated
- Bruce Millar
- G11 - INFORMATION STORAGE
Information Patent Grant
Timing vernier using a delay locked loop
- Patent number 8,013,646
- Issue date Sep 6, 2011
- MOSAID Technologies Incorporated
- Bruce Millar
- G01 - MEASURING TESTING
Information Patent Grant
Memory system having incorrupted strobe signals
- Patent number 7,889,580
- Issue date Feb 15, 2011
- Mosaid Technologies Incorporated
- Bruce Millar
- G11 - INFORMATION STORAGE
Information Patent Grant
Timing vernier using a delay locked loop
- Patent number 7,863,954
- Issue date Jan 4, 2011
- MOSAID Technologies Incorporated
- Bruce Millar
- G01 - MEASURING TESTING
Information Patent Grant
Dynamic impedance control for input/output buffers
- Patent number 7,834,654
- Issue date Nov 16, 2010
- MOSAID Technologies Incorporated
- Bruce Millar
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses for synchronous transfer of information
- Patent number 7,765,376
- Issue date Jul 27, 2010
- MOSAID Technologies Incorporated
- Peter Gillingham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
ASIC design using clock and power grid standard cell
- Patent number 7,761,831
- Issue date Jul 20, 2010
- Mosaid Technologies Incorporated
- Tony Mai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing vernier using a delay locked loop
- Patent number 7,671,650
- Issue date Mar 2, 2010
- MOSAID Technologies Incorporated
- Bruce Millar
- G01 - MEASURING TESTING
Information Patent Grant
Memory system having incorrupted strobe signals
- Patent number 7,652,932
- Issue date Jan 26, 2010
- MOSAID Technologies Incorporated
- Bruce Millar
- G11 - INFORMATION STORAGE
Information Patent Grant
Voltage down converter for high speed memory
- Patent number 7,593,281
- Issue date Sep 22, 2009
- MOSAID Technologies Incorporated
- Hong Beom Pyeon
- G11 - INFORMATION STORAGE
Information Patent Grant
Phase shifting in DLL/PLL
- Patent number 7,551,012
- Issue date Jun 23, 2009
- Mosaid Technologies Incorporated
- Huy Tuong Mai
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Timing vernier using a delay locked loop
- Patent number 7,391,247
- Issue date Jun 24, 2008
- Mosaid Technologies Incorporated
- Bruce Millar
- G01 - MEASURING TESTING
Information Patent Grant
High bandwidth memory interface
- Patent number 7,299,330
- Issue date Nov 20, 2007
- Mosaid Technologies Incorporated
- Peter Gillingham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Voltage down converter for high speed memory
- Patent number 7,248,531
- Issue date Jul 24, 2007
- Mosaid Technologies Incorporated
- Hong Beom Pyeon
- G11 - INFORMATION STORAGE
Information Patent Grant
Timing vernier using a delay locked loop
- Patent number 7,129,760
- Issue date Oct 31, 2006
- Mosaid Technologies Incorporated
- Bruce Millar
- G01 - MEASURING TESTING
Information Patent Grant
Timing vernier using a delay locked loop
- Patent number 7,038,517
- Issue date May 2, 2006
- Mosaid Technologies Incorporated
- Bruce Millar
- G01 - MEASURING TESTING
Information Patent Grant
Timing vernier using a delay locked loop
- Patent number 6,853,231
- Issue date Feb 8, 2005
- Mosaid Technologies Incorporated
- Bruce Millar
- G01 - MEASURING TESTING
Information Patent Grant
High bandwidth memory interface
- Patent number 6,779,097
- Issue date Aug 17, 2004
- Mosaid Technologies Incorporated
- Peter Gillingham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High bandwidth memory interface
- Patent number 6,510,503
- Issue date Jan 21, 2003
- Mosaid Technologies Incorporated
- Peter Gillingham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system having synchronous-link DRAM (SLDRAM) devices and con...
- Patent number 6,442,644
- Issue date Aug 27, 2002
- Advanced Memory International, Inc.
- David B. Gustavson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital delay locked loop
- Patent number 6,337,590
- Issue date Jan 8, 2002
- Mosaid Technologies Incorporated
- Bruce Millar
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
DYNAMIC IMPEDANCE CONTROL FOR INPUT/OUTPUT BUFFERS
- Publication number 20200266818
- Publication date Aug 20, 2020
- Conversant Intellectual Property Management Inc.
- Bruce MILLAR
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DYNAMIC IMPEDANCE CONTROL FOR INPUT/OUTPUT BUFFERS
- Publication number 20160277027
- Publication date Sep 22, 2016
- Conversant Intellectual Property Management Inc.
- Bruce MILLAR
- G11 - INFORMATION STORAGE
Information Patent Application
HIGH BANDWIDTH MEMORY INTERFACE
- Publication number 20150078057
- Publication date Mar 19, 2015
- Conversant Intellectual Property Management Inc.
- Peter B. GILLINGHAM
- G11 - INFORMATION STORAGE
Information Patent Application
DYNAMIC IMPEDANCE CONTROL FOR INPUT/OUTPUT BUFFERS
- Publication number 20150008956
- Publication date Jan 8, 2015
- Conversant Intellectual Property Management Inc.
- Bruce MILLAR
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
VOLTAGE DOWN CONVERTER FOR HIGH SPEED MEMORY
- Publication number 20140071781
- Publication date Mar 13, 2014
- MOSAID TECHNOLOGIES INCORPORATED
- Hong Beom PYEON
- G11 - INFORMATION STORAGE
Information Patent Application
HIGH BANDWIDTH MEMORY INTERFACE
- Publication number 20130329482
- Publication date Dec 12, 2013
- MOSAID TECHNOLOGIES INCORPORATED
- Peter B. GILLINGHAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY MODULE INCLUDING A PLURALITY OF SYNCHRONOUS MEMORY DEVICES
- Publication number 20130132761
- Publication date May 23, 2013
- MOSAID TECHNOLOGIES INCORPORATED
- Peter B. GILLINGHAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VOLTAGE DOWN CONVERTER FOR HIGH SPEED MEMORY
- Publication number 20120176118
- Publication date Jul 12, 2012
- MOSAID TECHNOLOGIES INCORPORATED
- Hong-Beom PYEON
- G11 - INFORMATION STORAGE
Information Patent Application
DYNAMIC IMPEDANCE CONTROL FOR INPUT/OUTPUT BUFFERS
- Publication number 20120019282
- Publication date Jan 26, 2012
- MOSAID TECHNOLOGIES INCORPORATED
- Bruce Millar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TIMING VERNIER USING A DELAY LOCKED LOOP
- Publication number 20110063006
- Publication date Mar 17, 2011
- MOSAID TECHNOLOGIES INCORPORATED
- Bruce Millar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DYNAMIC IMPEDANCE CONTROL FOR INPUT/OUTPUT BUFFERS
- Publication number 20110043246
- Publication date Feb 24, 2011
- MOSAID TECHNOLOGIES INCORPORATED
- Bruce Millar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
HIGH BANDWIDTH MEMORY INTERFACE
- Publication number 20100268906
- Publication date Oct 21, 2010
- MOSAID TECHNOLOGIES INCORPORATED
- Peter GILLINGHAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TIMING VERNIER USING A DELAY LOCKED LOOP
- Publication number 20100117698
- Publication date May 13, 2010
- MOSAID TECHNOLOGIES INCORPORATED
- Bruce Millar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MEMORY SYSTEM HAVING INCORRUPTED STROBE SIGNALS
- Publication number 20100097869
- Publication date Apr 22, 2010
- MOSAID TECHNOLOGIES INCORPORATED
- Bruce MILLAR
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
VOLTAGE DOWN CONVERTER FOR HIGH SPEED MEMORY
- Publication number 20090279375
- Publication date Nov 12, 2009
- MOSAID TECHNOLOGIES INCORPORATED
- Hong-Beom PYEON
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY SYSTEM HAVING INCORRUPTED STROBE SIGNALS
- Publication number 20090021998
- Publication date Jan 22, 2009
- MOSAID Technologies Incorporated
- Bruce MILLAR
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DYNAMIC IMPEDANCE CONTROL FOR INPUT/OUTPUT BUFFERS
- Publication number 20080303546
- Publication date Dec 11, 2008
- Mosaid Technologies Incorporated
- Bruce Millar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TIMING VERNIER USING A DELAY LOCKED LOOP
- Publication number 20080252344
- Publication date Oct 16, 2008
- MOSAID Technologies Incorporated
- Bruce Millar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PHASE SHIFTING IN DLL/PLL
- Publication number 20080238534
- Publication date Oct 2, 2008
- MOSAID Technologies Incorporated
- Huy Tuong MAI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
VOLTAGE DOWN CONVERTER FOR HIGH SPEED MEMORY
- Publication number 20080186790
- Publication date Aug 7, 2008
- MOSAID Technologies Incorporated
- Hong-Beom Pyeon
- G11 - INFORMATION STORAGE
Information Patent Application
High bandwidth memory interface
- Publication number 20080120458
- Publication date May 22, 2008
- PETER GILLINGHAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatuses for synchronous transfer of information
- Publication number 20080120457
- Publication date May 22, 2008
- MOSAID Technologies Incorporated
- Peter Gillingham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
High bandwidth memory interface
- Publication number 20080065820
- Publication date Mar 13, 2008
- PETER GILLINGHAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASIC design using clock and power grid standard cell
- Publication number 20070157144
- Publication date Jul 5, 2007
- Tony Mai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TIMING VERNIER USING A DELAY LOCKED LOOP
- Publication number 20070063750
- Publication date Mar 22, 2007
- MOSAID Technologies Incorporated
- Bruce MILLAR
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Voltage down converter for high speed memory
- Publication number 20070030749
- Publication date Feb 8, 2007
- Mosaid Technologies Incorporated
- Hong-Beom Pyeon
- G11 - INFORMATION STORAGE
Information Patent Application
Timing vernier using a delay locked loop
- Publication number 20060017484
- Publication date Jan 26, 2006
- MOSAID Technologies Incorporated
- Bruce Millar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Timing vernier using a delay locked loop
- Publication number 20050122144
- Publication date Jun 9, 2005
- MOSAID Technologies Incorporated
- Bruce Millar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
High bandwidth memory interface
- Publication number 20050081012
- Publication date Apr 14, 2005
- PETER GILLINGHAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Timing vernier using a delay locked loop
- Publication number 20040189372
- Publication date Sep 30, 2004
- Bruce Millar
- H03 - BASIC ELECTRONIC CIRCUITRY

Bruce MILLAR

Person

Patents Grantslast 30 patents

Dynamic impedance control for input/output buffers

Dynamic impedance control for input/output buffers

Dynamic impedance control for input/output buffers

Dynamic impedance control for input/output buffers

High bandwidth memory interface

Voltage down converter for high speed memory

High bandwidth memory interface

High bandwidth memory interface

Voltage down converter for high speed memory

Dynamic impedance control for input/output buffers

Timing vernier using a delay locked loop

Memory system having incorrupted strobe signals

Timing vernier using a delay locked loop

Dynamic impedance control for input/output buffers

Apparatuses for synchronous transfer of information

ASIC design using clock and power grid standard cell

Timing vernier using a delay locked loop

Memory system having incorrupted strobe signals

Voltage down converter for high speed memory

Phase shifting in DLL/PLL

Timing vernier using a delay locked loop

High bandwidth memory interface

Voltage down converter for high speed memory

Timing vernier using a delay locked loop

Timing vernier using a delay locked loop

Timing vernier using a delay locked loop

High bandwidth memory interface

High bandwidth memory interface

Memory system having synchronous-link DRAM (SLDRAM) devices and con...

Digital delay locked loop

Patents Applicationslast 30 patents

DYNAMIC IMPEDANCE CONTROL FOR INPUT/OUTPUT BUFFERS

DYNAMIC IMPEDANCE CONTROL FOR INPUT/OUTPUT BUFFERS

HIGH BANDWIDTH MEMORY INTERFACE

DYNAMIC IMPEDANCE CONTROL FOR INPUT/OUTPUT BUFFERS

VOLTAGE DOWN CONVERTER FOR HIGH SPEED MEMORY

HIGH BANDWIDTH MEMORY INTERFACE

MEMORY MODULE INCLUDING A PLURALITY OF SYNCHRONOUS MEMORY DEVICES

VOLTAGE DOWN CONVERTER FOR HIGH SPEED MEMORY

DYNAMIC IMPEDANCE CONTROL FOR INPUT/OUTPUT BUFFERS

TIMING VERNIER USING A DELAY LOCKED LOOP

DYNAMIC IMPEDANCE CONTROL FOR INPUT/OUTPUT BUFFERS

HIGH BANDWIDTH MEMORY INTERFACE

TIMING VERNIER USING A DELAY LOCKED LOOP

MEMORY SYSTEM HAVING INCORRUPTED STROBE SIGNALS

VOLTAGE DOWN CONVERTER FOR HIGH SPEED MEMORY

MEMORY SYSTEM HAVING INCORRUPTED STROBE SIGNALS

DYNAMIC IMPEDANCE CONTROL FOR INPUT/OUTPUT BUFFERS

TIMING VERNIER USING A DELAY LOCKED LOOP

PHASE SHIFTING IN DLL/PLL

VOLTAGE DOWN CONVERTER FOR HIGH SPEED MEMORY

High bandwidth memory interface

Apparatuses for synchronous transfer of information

High bandwidth memory interface

ASIC design using clock and power grid standard cell

TIMING VERNIER USING A DELAY LOCKED LOOP

Voltage down converter for high speed memory

Timing vernier using a delay locked loop

Timing vernier using a delay locked loop

High bandwidth memory interface

Timing vernier using a delay locked loop