Bryan Chin

Person

San Diago, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Local instruction ordering based on memory domains
- Patent number 10,782,896
- Issue date Sep 22, 2020
- Marvell Asia Pte, Ltd.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for allowing flexible chip configuration by ext...
- Patent number 10,666,682
- Issue date May 26, 2020
- Marvell Asia Pte, Ltd.
- Isam Akkawi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed interrupt scheme in a multi-processor system
- Patent number 10,394,730
- Issue date Aug 27, 2019
- Cavium, LLC
- Bryan W. Chin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for managing complex genomic data workflows
- Patent number 10,331,848
- Issue date Jun 25, 2019
- ONRAMP BIOINFORMATICS, INC.
- Timothy Wesselman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Local ordering of instructions in a computing system
- Patent number 10,216,430
- Issue date Feb 26, 2019
- Cavium, LLC
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Collapsed address translation with multiple page sizes
- Patent number 10,042,778
- Issue date Aug 7, 2018
- Cavium, Inc.
- Shubhendu S. Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for determining metric for selective caching
- Patent number 10,007,614
- Issue date Jun 26, 2018
- Cavium, Inc.
- Xiaodong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed timer subsystem
- Patent number 9,928,193
- Issue date Mar 27, 2018
- Cavium, Inc.
- Frank Worrell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for distributed instruction trace in a process...
- Patent number 9,703,669
- Issue date Jul 11, 2017
- Cavium, Inc.
- Gerald Lampert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Collapsed address translation with multiple page sizes
- Patent number 9,645,941
- Issue date May 9, 2017
- Cavium, Inc.
- Shubhendu S. Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Merged TLB structure for multiple sequential address translations
- Patent number 9,639,476
- Issue date May 2, 2017
- Cavium, Inc.
- Bryan W. Chin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed timer subsystem across multiple devices
- Patent number 9,568,944
- Issue date Feb 14, 2017
- Cavium, Inc.
- Frank Worrell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
QoS based dynamic execution engine selection
- Patent number 9,495,161
- Issue date Nov 15, 2016
- Cavium, Inc.
- Najeeb I. Ansari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Debug interface for multiple CPU cores
- Patent number 9,404,970
- Issue date Aug 2, 2016
- Cavium, Inc.
- Teng Chiang Lin
- G01 - MEASURING TESTING
Information Patent Grant
Inter-chip interconnect protocol for a multi-chip system
- Patent number 9,372,800
- Issue date Jun 21, 2016
- Cavium, Inc.
- Isam Akkawi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Maintenance of cache and tags in a translation lookaside buffer
- Patent number 9,268,694
- Issue date Feb 23, 2016
- Cavium, Inc.
- Wilson P. Snyder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Translation bypass in multi-stage address translation
- Patent number 9,208,103
- Issue date Dec 8, 2015
- Cavium, Inc.
- Richard E. Kessler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
QoS based dynamic execution engine selection
- Patent number 9,129,060
- Issue date Sep 8, 2015
- Cavium, Inc.
- Najeeb I. Ansari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor with dedicated virtual functions and dynamic assignment o...
- Patent number 9,128,769
- Issue date Sep 8, 2015
- Cavium, Inc.
- Jeffrey Schroeder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed variable bandwidth ring-based system
- Patent number 8,989,220
- Issue date Mar 24, 2015
- Cavium, Inc.
- Paul G. Scrobohaci
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Fast invalidation for cache coherency in distributed shared memory...
- Patent number 7,613,882
- Issue date Nov 3, 2009
- 3 Leaf Systems
- Isam Akkawi
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SYSTEMS AND METHODS FOR ALLOWING FLEXIBLE CHIP CONFIGURATION BY EXT...
- Publication number 20200252434
- Publication date Aug 6, 2020
- Marvell Asia Pte, Ltd. (Registration No. 199702379M)
- Isam Akkawi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR MANAGING COMPLEX GENOMIC DATA WORKFLOWS
- Publication number 20190287655
- Publication date Sep 19, 2019
- ONRAMP BIOINFORMATICS, INC.
- Timothy Wesselman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOCAL INSTRUCTION ORDERING BASED ON MEMORY DOMAINS
- Publication number 20190138232
- Publication date May 9, 2019
- Cavium, LLC
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR MANAGING COMPLEX GENOMIC DATA WORKFLOWS
- Publication number 20180218114
- Publication date Aug 2, 2018
- ONRAMP BIOINFORMATICS, INC.
- Timothy Wesselman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR DETERMINING METRIC FOR SELECTIVE CACHING
- Publication number 20170220477
- Publication date Aug 3, 2017
- Cavium, Inc.
- Xiaodong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Collapsed Address Translation With Multiple Page Sizes
- Publication number 20170206171
- Publication date Jul 20, 2017
- Cavium, Inc.
- Shubhendu S. Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOCAL INSTRUCTION ORDERING
- Publication number 20170003905
- Publication date Jan 5, 2017
- Cavium, Inc.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTED TIMER SUBSYSTEM
- Publication number 20160140066
- Publication date May 19, 2016
- Cavium, Inc.
- Frank Worrell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTED TIMER SUBSYSTEM ACROSS MULTIPLE DEVICES
- Publication number 20160139625
- Publication date May 19, 2016
- Cavium, Inc.
- Frank Worrell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEBUG INTERFACE FOR MULTIPLE CPU CORES
- Publication number 20160139201
- Publication date May 19, 2016
- Cavium, Inc.
- Teng Chiang Lin
- G01 - MEASURING TESTING
Information Patent Application
DISTRIBUTED INTERRUPT SCHEME IN A MULTI-PROCESSOR SYSTEM
- Publication number 20160140064
- Publication date May 19, 2016
- Cavium, Inc.
- Bryan W. CHIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR DISTRIBUTED INSTRUCTION TRACE IN A PROCESS...
- Publication number 20160140014
- Publication date May 19, 2016
- Cavium, Inc.
- Gerald Lampert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR ALLOWING FLEXIBLE CHIP CONFIGURATION BY EXT...
- Publication number 20160112264
- Publication date Apr 21, 2016
- Cavium, Inc.
- ISAM AKKAWI
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
QoS Based Dynamic Execution Engine Selection
- Publication number 20150363200
- Publication date Dec 17, 2015
- Cavium, Inc.
- Najeeb I. Ansari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTER-CHIP INTERCONNECT PROTOCOL FOR A MULTI-CHIP SYSTEM
- Publication number 20150254183
- Publication date Sep 10, 2015
- Cavium, Inc.
- Isam Akkawi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Merged TLB Structure For Multiple Sequential Address Translations
- Publication number 20150089116
- Publication date Mar 26, 2015
- Cavium, Inc.
- Bryan W. Chin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Maintenance Of Cache And Tags In A Translation Lookaside Buffer
- Publication number 20150089147
- Publication date Mar 26, 2015
- Cavium, Inc.
- Wilson P. Snyder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Translation Bypass In Multi-Stage Address Translation
- Publication number 20150089150
- Publication date Mar 26, 2015
- Cavium, Inc.
- Richard E. Kessler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Collapsed Address Translation With Multiple Page Sizes
- Publication number 20150089184
- Publication date Mar 26, 2015
- Cavium, Inc.
- Shubhendu S. Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
High Speed Variable Bandwidth Ring-Based System
- Publication number 20130315236
- Publication date Nov 28, 2013
- Cavium, Inc.
- Paul G. Scrobohaci
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
QOS BASED DYNAMIC EXECUTION ENGINE SELECTION
- Publication number 20130097350
- Publication date Apr 18, 2013
- Cavium, Inc.
- Najeeb I. Ansari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR WITH DEDICATED VIRTUAL FUNCTIONS AND DYNAMIC ASSIGNMENT O...
- Publication number 20130097598
- Publication date Apr 18, 2013
- Cavium, Inc.
- Jeffrey Schroeder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Block Caching for Cache-Coherent Distributed Shared Memory
- Publication number 20110004729
- Publication date Jan 6, 2011
- 3Leaf Systems, Inc.
- Isam Akkawi
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Local instruction ordering based on memory domains

Systems and methods for allowing flexible chip configuration by ext...

Distributed interrupt scheme in a multi-processor system

Method for managing complex genomic data workflows

Local ordering of instructions in a computing system

Collapsed address translation with multiple page sizes

Method and apparatus for determining metric for selective caching

Distributed timer subsystem

Apparatus and method for distributed instruction trace in a process...

Collapsed address translation with multiple page sizes

Merged TLB structure for multiple sequential address translations

Distributed timer subsystem across multiple devices

QoS based dynamic execution engine selection

Debug interface for multiple CPU cores

Inter-chip interconnect protocol for a multi-chip system

Maintenance of cache and tags in a translation lookaside buffer

Translation bypass in multi-stage address translation

QoS based dynamic execution engine selection

Processor with dedicated virtual functions and dynamic assignment o...

High speed variable bandwidth ring-based system

Fast invalidation for cache coherency in distributed shared memory...

Patents Applicationslast 30 patents

SYSTEMS AND METHODS FOR ALLOWING FLEXIBLE CHIP CONFIGURATION BY EXT...

METHOD FOR MANAGING COMPLEX GENOMIC DATA WORKFLOWS

LOCAL INSTRUCTION ORDERING BASED ON MEMORY DOMAINS

METHOD FOR MANAGING COMPLEX GENOMIC DATA WORKFLOWS

METHOD AND APPARATUS FOR DETERMINING METRIC FOR SELECTIVE CACHING

Collapsed Address Translation With Multiple Page Sizes

LOCAL INSTRUCTION ORDERING

DISTRIBUTED TIMER SUBSYSTEM

DISTRIBUTED TIMER SUBSYSTEM ACROSS MULTIPLE DEVICES

DEBUG INTERFACE FOR MULTIPLE CPU CORES

DISTRIBUTED INTERRUPT SCHEME IN A MULTI-PROCESSOR SYSTEM

APPARATUS AND METHOD FOR DISTRIBUTED INSTRUCTION TRACE IN A PROCESS...

SYSTEMS AND METHODS FOR ALLOWING FLEXIBLE CHIP CONFIGURATION BY EXT...

QoS Based Dynamic Execution Engine Selection

INTER-CHIP INTERCONNECT PROTOCOL FOR A MULTI-CHIP SYSTEM

Merged TLB Structure For Multiple Sequential Address Translations

Maintenance Of Cache And Tags In A Translation Lookaside Buffer

Translation Bypass In Multi-Stage Address Translation

Collapsed Address Translation With Multiple Page Sizes

High Speed Variable Bandwidth Ring-Based System

QOS BASED DYNAMIC EXECUTION ENGINE SELECTION

PROCESSOR WITH DEDICATED VIRTUAL FUNCTIONS AND DYNAMIC ASSIGNMENT O...

Block Caching for Cache-Coherent Distributed Shared Memory