Bryan Cope

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Computer architecture with disaggregated memory and high-bandwidth...
- Patent number 12,117,930
- Issue date Oct 15, 2024
- Luminous Computing, Inc.
- David Cureton Baker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer architecture with disaggregated memory and high-bandwidth...
- Patent number 12,099,724
- Issue date Sep 24, 2024
- Luminous Computing, Inc.
- David Cureton Baker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Self-timed processors implemented with multi-rail null convention l...
- Patent number 10,951,212
- Issue date Mar 16, 2021
- Eta Compute, Inc.
- Chao Xu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Interface from null convention logic to synchronous memory
- Patent number 10,642,759
- Issue date May 5, 2020
- Eta Compute, Inc.
- Vidura Manu Wijayasekara
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual-rail delay insensitive asynchronous logic processor with singl...
- Patent number 10,338,930
- Issue date Jul 2, 2019
- Eta Compute, Inc.
- Ben Melton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Self-timed processors implemented with multi-rail null convention l...
- Patent number 10,205,453
- Issue date Feb 12, 2019
- Eta Compute, Inc.
- Chao Xu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for controlling memory operations
- Patent number 7,752,373
- Issue date Jul 6, 2010
- SigmaTel, Inc.
- Bryan Cope
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple stage attenuator
- Patent number 6,980,056
- Issue date Dec 27, 2005
- Cirrus Logic, Inc.
- Mark Alexander
- G10 - MUSICAL INSTRUMENTS ACOUSTICS
Information Patent Grant
Methods and apparatus for pipelined bus
- Patent number 6,912,608
- Issue date Jun 28, 2005
- PTS Corporation
- Edward A. Wolff
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuits and methods for implementing audio Codecs and systems usin...
- Patent number 6,259,957
- Issue date Jul 10, 2001
- Cirrus Logic, Inc.
- Mark Alexander
- G10 - MUSICAL INSTRUMENTS ACOUSTICS

Patents Applicationslast 30 patents

Information Patent Application
COMPUTER ARCHITECTURE WITH DISAGGREGATED MEMORY AND HIGH-BANDWIDTH...
- Publication number 20240078175
- Publication date Mar 7, 2024
- Luminous Computing, Inc.
- David Cureton BAKER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTER ARCHITECTURE WITH DISAGGREGATED MEMORY AND HIGH-BANDWIDTH...
- Publication number 20240079081
- Publication date Mar 7, 2024
- Luminous Computing, Inc.
- David Cureton BAKER
- G11 - INFORMATION STORAGE
Information Patent Application
COMPUTER ARCHITECTURE WITH DISAGGREGATED MEMORY AND HIGH-BANDWIDTH...
- Publication number 20240078016
- Publication date Mar 7, 2024
- Luminous Computing, Inc.
- David Cureton BAKER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELF-TIMED PROCESSORS IMPLEMENTED WITH MULTI-RAIL NULL CONVENTION L...
- Publication number 20190190520
- Publication date Jun 20, 2019
- Eta Compute, Inc.
- Chao Xu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DUAL-RAIL DELAY INSENSITIVE ASYNCHRONOUS LOGIC PROCESSOR WITH SINGL...
- Publication number 20190004811
- Publication date Jan 3, 2019
- Eta Compute, Inc.
- Ben Melton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL-RAIL DELAY INSENSITIVE ASYNCHRONOUS LOGIC PROCESSOR WITH SINGL...
- Publication number 20190004812
- Publication date Jan 3, 2019
- Eta Compute, Inc.
- Ben Melton
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INTERFACE FROM NULL CONVENTION LOGIC TO SYNCHRONOUS MEMORY
- Publication number 20180300263
- Publication date Oct 18, 2018
- Eta Compute, Inc.
- Vidura Manu Wijayasekara
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELF-TIMED PROCESSORS IMPLEMENTED WITH MULTI-RAIL NULL CONVENTION L...
- Publication number 20180294810
- Publication date Oct 11, 2018
- Eta Compute, Inc.
- Chao Xu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
System and method for controlling memory operations
- Publication number 20080195806
- Publication date Aug 14, 2008
- SigmaTel, Inc.
- Bryan Cope
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Device, system and method for controlling memory operations
- Publication number 20080189479
- Publication date Aug 7, 2008
- SigmaTel, Inc.
- Bryan Cope
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatus for pipelined bus
- Publication number 20030046462
- Publication date Mar 6, 2003
- BOPS, INC.
- Edward A. Wolff
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Computer architecture with disaggregated memory and high-bandwidth...

Computer architecture with disaggregated memory and high-bandwidth...

Self-timed processors implemented with multi-rail null convention l...

Interface from null convention logic to synchronous memory

Dual-rail delay insensitive asynchronous logic processor with singl...

Self-timed processors implemented with multi-rail null convention l...

System and method for controlling memory operations

Multiple stage attenuator

Methods and apparatus for pipelined bus

Circuits and methods for implementing audio Codecs and systems usin...

Patents Applicationslast 30 patents

COMPUTER ARCHITECTURE WITH DISAGGREGATED MEMORY AND HIGH-BANDWIDTH...

COMPUTER ARCHITECTURE WITH DISAGGREGATED MEMORY AND HIGH-BANDWIDTH...

COMPUTER ARCHITECTURE WITH DISAGGREGATED MEMORY AND HIGH-BANDWIDTH...

SELF-TIMED PROCESSORS IMPLEMENTED WITH MULTI-RAIL NULL CONVENTION L...

DUAL-RAIL DELAY INSENSITIVE ASYNCHRONOUS LOGIC PROCESSOR WITH SINGL...

DUAL-RAIL DELAY INSENSITIVE ASYNCHRONOUS LOGIC PROCESSOR WITH SINGL...

INTERFACE FROM NULL CONVENTION LOGIC TO SYNCHRONOUS MEMORY

SELF-TIMED PROCESSORS IMPLEMENTED WITH MULTI-RAIL NULL CONVENTION L...

System and method for controlling memory operations

Device, system and method for controlling memory operations

Methods and apparatus for pipelined bus