Bryan L. Spry

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Power control techniques for integrated PCIe controllers
- Patent number 10,496,152
- Issue date Dec 3, 2019
- Intel Corporation
- Bryan L. Spry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for dynamically adjusting voltage reference to...
- Patent number 10,347,319
- Issue date Jul 9, 2019
- Intel Corporation
- Christopher P. Mozak
- G11 - INFORMATION STORAGE
Information Patent Grant
Method, apparatus and system for configuring a protocol stack of an...
- Patent number 10,282,341
- Issue date May 7, 2019
- Intel Corporation
- Bryan L. Spry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, apparatus and system for single-ended communication of tran...
- Patent number 9,910,814
- Issue date Mar 6, 2018
- Intel Corporation
- Bryan L. Spry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, apparatus and system for configuring a protocol stack of an...
- Patent number 9,734,116
- Issue date Aug 15, 2017
- Intel Corporation
- Bryan L. Spry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for dynamically adjusting voltage reference to...
- Patent number 9,373,365
- Issue date Jun 21, 2016
- Intel Corporation
- Christopher P. Mozak
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for dynamically adjusting voltage reference to...
- Patent number 9,330,734
- Issue date May 3, 2016
- Intel Corporation
- Christopher P. Mozak
- G11 - INFORMATION STORAGE
Information Patent Grant
Robust memory link testing using memory controller
- Patent number 8,868,992
- Issue date Oct 21, 2014
- Intel Corporation
- Bryan L. Spry
- G11 - INFORMATION STORAGE
Information Patent Grant
Active training of memory command timing
- Patent number 8,819,474
- Issue date Aug 26, 2014
- Intel Corporation
- Theodore Z. Schoenborn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for dynamically adjusting voltage reference to...
- Patent number 8,582,374
- Issue date Nov 12, 2013
- Intel Corporation
- Christopher Mozak
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for evaluating effects of signal phase difference...
- Patent number 8,331,176
- Issue date Dec 11, 2012
- Intel Corporation
- Christopher P. Mozak
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory link training
- Patent number 7,886,174
- Issue date Feb 8, 2011
- Intel Corporation
- Bryan L. Spry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method to reduce memory latency in microprocessor system...
- Patent number 7,779,188
- Issue date Aug 17, 2010
- Intel Corporation
- Bryan L. Spry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Monitor implementation in a multicore processor with inclusive LLC
- Patent number 7,590,805
- Issue date Sep 15, 2009
- Intel Corporation
- Krishnakanth V. Sistla
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD, APPARATUS AND SYSTEM FOR CONFIGURING A PROTOCOL STACK OF AN...
- Publication number 20180210857
- Publication date Jul 26, 2018
- Intel Corporation
- Bryan L. Spry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, APPARATUS, AND SYSTEM FOR SIGNAL EQUALIZATION
- Publication number 20170346596
- Publication date Nov 30, 2017
- Intel Corporation
- Nathaniel L. Desimone
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR DYNAMICALLY ADJUSTING VOLTAGE REFERENCE TO...
- Publication number 20160232962
- Publication date Aug 11, 2016
- Intel Corporation
- Christopher P. Mozak
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD, APPARATUS AND SYSTEM FOR CONFIGURING A PROTOCOL STACK OF AN...
- Publication number 20150269108
- Publication date Sep 24, 2015
- Bryan L. Spry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, APPARATUS AND SYSTEM FOR SINGLE-ENDED COMMUNICATION OF TRAN...
- Publication number 20150269109
- Publication date Sep 24, 2015
- Bryan L. Spry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER CONTROL TECHNIQUES FOR INTEGRATED PCIE CONTROLLERS
- Publication number 20150095687
- Publication date Apr 2, 2015
- BRYAN L. SPRY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR DYNAMICALLY ADJUSTING VOLTAGE REFERENCE TO...
- Publication number 20140119137
- Publication date May 1, 2014
- Christopher P. MOZAK
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR DYNAMICALLY ADJUSTING VOLTAGE REFERENCE TO...
- Publication number 20140063982
- Publication date Mar 6, 2014
- Christopher P. MOZAK
- G11 - INFORMATION STORAGE
Information Patent Application
ROBUST MEMORY LINK TESTING USING MEMORY CONTROLLER
- Publication number 20110161752
- Publication date Jun 30, 2011
- BRYAN L. SPRY
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR DYNAMICALLY ADJUSTING VOLTAGE REFERENCE TO...
- Publication number 20110141827
- Publication date Jun 16, 2011
- Christopher Mozak
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND SYSTEM FOR EVALUATING EFFECTS OF SIGNAL PHASE DIFFERENCE...
- Publication number 20110131458
- Publication date Jun 2, 2011
- Christopher P. Mozak
- G11 - INFORMATION STORAGE
Information Patent Application
ACTIVE TRAINING OF MEMORY COMMAND TIMING
- Publication number 20100257397
- Publication date Oct 7, 2010
- Theodore Z. Schoenborn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY LINK TRAINING
- Publication number 20090006776
- Publication date Jan 1, 2009
- Bryan L. Spry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism for write optimization to a memory device
- Publication number 20080162799
- Publication date Jul 3, 2008
- Bryan Spry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Monitor implementation in a multicore processor with inclusive LLC
- Publication number 20070156971
- Publication date Jul 5, 2007
- Krishnakanth V. Sistla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Enforcing global ordering using an inter-queue ordering mechanism
- Publication number 20070005865
- Publication date Jan 4, 2007
- Bryan L. Spry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method to reduce memory latency in microprocessor system...
- Publication number 20060218334
- Publication date Sep 28, 2006
- Bryan L. Spry
- G06 - COMPUTING CALCULATING COUNTING

Bryan L. Spry

Person

Patents Grantslast 30 patents

Power control techniques for integrated PCIe controllers

Method and apparatus for dynamically adjusting voltage reference to...

Method, apparatus and system for configuring a protocol stack of an...

Method, apparatus and system for single-ended communication of tran...

Method, apparatus and system for configuring a protocol stack of an...

Method and apparatus for dynamically adjusting voltage reference to...

Method and apparatus for dynamically adjusting voltage reference to...

Robust memory link testing using memory controller

Active training of memory command timing

Method and apparatus for dynamically adjusting voltage reference to...

Method and system for evaluating effects of signal phase difference...

Memory link training

System and method to reduce memory latency in microprocessor system...

Monitor implementation in a multicore processor with inclusive LLC

Patents Applicationslast 30 patents

METHOD, APPARATUS AND SYSTEM FOR CONFIGURING A PROTOCOL STACK OF AN...

METHOD, APPARATUS, AND SYSTEM FOR SIGNAL EQUALIZATION

METHOD AND APPARATUS FOR DYNAMICALLY ADJUSTING VOLTAGE REFERENCE TO...

METHOD, APPARATUS AND SYSTEM FOR CONFIGURING A PROTOCOL STACK OF AN...

METHOD, APPARATUS AND SYSTEM FOR SINGLE-ENDED COMMUNICATION OF TRAN...

POWER CONTROL TECHNIQUES FOR INTEGRATED PCIE CONTROLLERS

METHOD AND APPARATUS FOR DYNAMICALLY ADJUSTING VOLTAGE REFERENCE TO...

METHOD AND APPARATUS FOR DYNAMICALLY ADJUSTING VOLTAGE REFERENCE TO...

ROBUST MEMORY LINK TESTING USING MEMORY CONTROLLER

METHOD AND APPARATUS FOR DYNAMICALLY ADJUSTING VOLTAGE REFERENCE TO...

METHOD AND SYSTEM FOR EVALUATING EFFECTS OF SIGNAL PHASE DIFFERENCE...

ACTIVE TRAINING OF MEMORY COMMAND TIMING

MEMORY LINK TRAINING

Mechanism for write optimization to a memory device

Monitor implementation in a multicore processor with inclusive LLC

Enforcing global ordering using an inter-queue ordering mechanism

System and method to reduce memory latency in microprocessor system...