Bryant E. Bigbee

Person

Scottsdale, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Hardware apparatuses and methods for memory corruption detection
- Patent number 11,645,135
- Issue date May 9, 2023
- Intel Corporation
- Tomer Stark
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware apparatuses and methods for memory corruption detection
- Patent number 10,776,190
- Issue date Sep 15, 2020
- Intel Corporation
- Tomer Stark
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for instruction set based thread execution on a plurality...
- Patent number 10,452,403
- Issue date Oct 22, 2019
- Intel Corporation
- Hong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Providing a secure execution mode in a pre-boot environment
- Patent number 10,275,598
- Issue date Apr 30, 2019
- Intel Corporation
- Vincent J. Zimmer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware apparatuses and methods for memory corruption detection
- Patent number 10,162,694
- Issue date Dec 25, 2018
- Intel Corporation
- Tomer Stark
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for instruction set based thread execution of a plurality...
- Patent number 9,990,206
- Issue date Jun 5, 2018
- Intel Corporation
- Hong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus, system, and method for persistent user-level thread
- Patent number 9,875,102
- Issue date Jan 23, 2018
- Intel Corporation
- Gautham Chinya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus, system, and method for persistent user-level thread
- Patent number 9,766,891
- Issue date Sep 19, 2017
- Intel Corporation
- Gautham Chinya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for instruction set based thread execution on a plurality...
- Patent number 9,720,697
- Issue date Aug 1, 2017
- Intel Corporation
- Hong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction set architecture-based inter-sequencer communications w...
- Patent number 9,588,771
- Issue date Mar 7, 2017
- Intel Corporation
- Hong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction set architecture-based inter-sequencer communications w...
- Patent number 9,459,874
- Issue date Oct 4, 2016
- Intel Corporation
- Hong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hetergeneous processor apparatus and method
- Patent number 9,448,829
- Issue date Sep 20, 2016
- Intel Corporation
- Paolo Narvaez
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus, system, and method for persistent user-level thread
- Patent number 9,383,997
- Issue date Jul 5, 2016
- Intel Corporation
- Gautham Chinya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism to schedule threads on OS-sequestered sequencers without...
- Patent number 9,069,605
- Issue date Jun 30, 2015
- Intel Corporation
- Richard A. Hankins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System to profile and optimize user software in a managed run-time...
- Patent number 9,063,804
- Issue date Jun 23, 2015
- Intel Corporation
- Chris J. Newburn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Providing a secure execution mode in a pre-boot environment
- Patent number 9,026,773
- Issue date May 5, 2015
- Intel Corporation
- Vincent J. Zimmer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction set architecture-based inter-sequencer communications w...
- Patent number 8,914,618
- Issue date Dec 16, 2014
- Intel Corporation
- Hong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for monitoring instruction set based thread execution on...
- Patent number 8,887,174
- Issue date Nov 11, 2014
- Intel Corporation
- Richard A. Hankins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable event-driven yield mechanism
- Patent number 8,762,694
- Issue date Jun 24, 2014
- Intel Corporation
- Xiang Zou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for instruction set based thread execution on a plurality...
- Patent number 8,719,819
- Issue date May 6, 2014
- Intel Corporation
- Hong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Context state management for processor feature sets
- Patent number 8,677,163
- Issue date Mar 18, 2014
- Intel Corporation
- Don Van Dyke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism to handle events in a machine with isolated execution
- Patent number 8,671,275
- Issue date Mar 11, 2014
- Intel Corporation
- Francis X. McKeen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Context state management for processor feature sets
- Patent number 8,631,261
- Issue date Jan 14, 2014
- Intel Corporation
- Don A. Van Dyke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism to schedule threads on OS-sequestered sequencers without...
- Patent number 8,607,235
- Issue date Dec 10, 2013
- Intel Corporation
- Richard A. Hankins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System to profile and optimize user software in a managed run-time...
- Patent number 8,566,567
- Issue date Oct 22, 2013
- Intel Corporation
- Chris J. Newburn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism to handle events in a machine with isolated execution
- Patent number 8,522,044
- Issue date Aug 27, 2013
- Intel Corporation
- Francis X. McKeen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transparent support for operating system services for a sequestered...
- Patent number 8,516,483
- Issue date Aug 20, 2013
- Intel Corporation
- Gautham Chinya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus, system, and method for persistent user-level thread
- Patent number 8,479,217
- Issue date Jul 2, 2013
- Intel Corporation
- Gautham Chinya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism to handle events in a machine with isolated execution
- Patent number 8,458,464
- Issue date Jun 4, 2013
- Intel Corporation
- Francis X. McKeen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Primitives to enhance thread-level speculation
- Patent number 8,332,619
- Issue date Dec 11, 2012
- Intel Corporation
- Quinn A. Jacobson
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
HARDWARE APPARATUSES AND METHODS FOR MEMORY CORRUPTION DETECTION
- Publication number 20230273846
- Publication date Aug 31, 2023
- Intel Corporation
- Tomer Stark
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE APPARATUSES AND METHODS FOR MEMORY CORRUPTION DETECTION
- Publication number 20210141683
- Publication date May 13, 2021
- Intel Corporation
- Tomer Stark
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE APPARATUSES AND METHODS FOR MEMORY CORRUPTION DETECTION
- Publication number 20190235948
- Publication date Aug 1, 2019
- Intel Corporation
- Tomer Stark
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE APPARATUSES AND METHODS FOR MEMORY CORRUPTION DETECTION
- Publication number 20170177429
- Publication date Jun 22, 2017
- Tomer Stark
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus, System, And Method For Persistent User-Level Thread
- Publication number 20170102944
- Publication date Apr 13, 2017
- Intel Corporation
- Gautham Chinya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISM FOR INSTRUCTION SET BASED THREAD EXECUTION ON A PLURALITY...
- Publication number 20170010895
- Publication date Jan 12, 2017
- Intel Corporation
- Hong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus, System, And Method For Persistent User-Level Thread
- Publication number 20160274910
- Publication date Sep 22, 2016
- Intel Corporation
- Gautham Chinya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISM FOR INSTRUCTION SET BASED THREAD EXECUTION ON A PLURALITY...
- Publication number 20160019067
- Publication date Jan 21, 2016
- Hong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Providing a Secure Execution Mode in a Pre-Boot Environment
- Publication number 20150213269
- Publication date Jul 30, 2015
- Intel Corporation
- Vincent J. Zimmer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instruction Set Architecture-Based Inter-Sequencer Communications W...
- Publication number 20150070368
- Publication date Mar 12, 2015
- Intel Corporation
- Hong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HETERGENEOUS PROCESSOR APPARATUS AND METHOD
- Publication number 20140189297
- Publication date Jul 3, 2014
- Paolo Narvaez
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISM TO SCHEDULE THREADS ON OS-SEQUESTERED SEQUENCERS WITHOUT...
- Publication number 20140115594
- Publication date Apr 24, 2014
- Richard A. Hankins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM TO PROFILE AND OPTIMIZE USER SOFTWARE IN A MANAGED RUN-TIME...
- Publication number 20140089942
- Publication date Mar 27, 2014
- Chris J. Newburn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus, System, And Method For Persistent User-Level Thread
- Publication number 20130275735
- Publication date Oct 17, 2013
- Gautham Chinya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISM FOR INSTRUCTION SET BASED THREAD EXECUTION OF A PLURALITY...
- Publication number 20130219399
- Publication date Aug 22, 2013
- Hong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTEXT STATE MANAGEMENT FOR PROCESSOR FEATURE SETS
- Publication number 20130219154
- Publication date Aug 22, 2013
- Don A. Van Dyke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION SET ARCHITECTURE-BASED INTER-SEQUENCER COMMUNICATIONS W...
- Publication number 20130205122
- Publication date Aug 8, 2013
- Hong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRIMITIVES TO ENHANCE THREAD-LEVEL SPECULATION
- Publication number 20130073835
- Publication date Mar 21, 2013
- Quinn A. Jacobson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISM FOR INSTRUCTION SET BASED THREAD EXECUTION ON A PLURALITY...
- Publication number 20130054940
- Publication date Feb 28, 2013
- Hong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTEXT STATE MANAGEMENT FOR PROCESSOR FEATURE SETS
- Publication number 20130042093
- Publication date Feb 14, 2013
- Don A. Van Dyke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System To Profile And Optimize User Software In A Managed Run-Time...
- Publication number 20130031557
- Publication date Jan 31, 2013
- Chris J. Newburn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRIMITIVES TO ENHANCE THREAD-LEVEL SPECULATION
- Publication number 20120084536
- Publication date Apr 5, 2012
- Quinn A. Jacobson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism for Monitoring Instruction Set Based Thread Execution on...
- Publication number 20120017221
- Publication date Jan 19, 2012
- Richard A. Hankins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus, System, And Method For Persistent User-Level Thread
- Publication number 20110314480
- Publication date Dec 22, 2011
- Gautham Chinya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Providing a secure execution mode in a pre-boot environment
- Publication number 20110271090
- Publication date Nov 3, 2011
- Vincent J. Zimmer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRIMITIVES TO ENHANCE THREAD-LEVEL SPECULATION
- Publication number 20110087867
- Publication date Apr 14, 2011
- Quinn A. Jacobson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISM TO HANDLE EVENTS IN A MACHINE WITH ISOLATED EXECUTION
- Publication number 20100332760
- Publication date Dec 30, 2010
- Francis X. McKeen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISM TO HANDLE EVENTS IN A MACHINE WITH ISOLATED EXECUTION
- Publication number 20100325354
- Publication date Dec 23, 2010
- Francis X. McKeen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISM TO HANDLE EVENTS IN A MACHINE WITH ISOLATED EXECUTION
- Publication number 20100325445
- Publication date Dec 23, 2010
- Francis X. McKeen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Technique for context state management
- Publication number 20080133898
- Publication date Jun 5, 2008
- Chris J. Newburn
- G06 - COMPUTING CALCULATING COUNTING

Bryant E. Bigbee

Person

Patents Grantslast 30 patents

Hardware apparatuses and methods for memory corruption detection

Hardware apparatuses and methods for memory corruption detection

Mechanism for instruction set based thread execution on a plurality...

Providing a secure execution mode in a pre-boot environment

Hardware apparatuses and methods for memory corruption detection

Mechanism for instruction set based thread execution of a plurality...

Apparatus, system, and method for persistent user-level thread

Apparatus, system, and method for persistent user-level thread

Mechanism for instruction set based thread execution on a plurality...

Instruction set architecture-based inter-sequencer communications w...

Instruction set architecture-based inter-sequencer communications w...

Hetergeneous processor apparatus and method

Apparatus, system, and method for persistent user-level thread

Mechanism to schedule threads on OS-sequestered sequencers without...

System to profile and optimize user software in a managed run-time...

Providing a secure execution mode in a pre-boot environment

Instruction set architecture-based inter-sequencer communications w...

Mechanism for monitoring instruction set based thread execution on...

Programmable event-driven yield mechanism

Mechanism for instruction set based thread execution on a plurality...

Context state management for processor feature sets

Mechanism to handle events in a machine with isolated execution

Context state management for processor feature sets

Mechanism to schedule threads on OS-sequestered sequencers without...

System to profile and optimize user software in a managed run-time...

Mechanism to handle events in a machine with isolated execution

Transparent support for operating system services for a sequestered...

Apparatus, system, and method for persistent user-level thread

Mechanism to handle events in a machine with isolated execution

Primitives to enhance thread-level speculation

Patents Applicationslast 30 patents

HARDWARE APPARATUSES AND METHODS FOR MEMORY CORRUPTION DETECTION

HARDWARE APPARATUSES AND METHODS FOR MEMORY CORRUPTION DETECTION

HARDWARE APPARATUSES AND METHODS FOR MEMORY CORRUPTION DETECTION

HARDWARE APPARATUSES AND METHODS FOR MEMORY CORRUPTION DETECTION

Apparatus, System, And Method For Persistent User-Level Thread

MECHANISM FOR INSTRUCTION SET BASED THREAD EXECUTION ON A PLURALITY...

Apparatus, System, And Method For Persistent User-Level Thread

MECHANISM FOR INSTRUCTION SET BASED THREAD EXECUTION ON A PLURALITY...

Providing a Secure Execution Mode in a Pre-Boot Environment

Instruction Set Architecture-Based Inter-Sequencer Communications W...

HETERGENEOUS PROCESSOR APPARATUS AND METHOD

MECHANISM TO SCHEDULE THREADS ON OS-SEQUESTERED SEQUENCERS WITHOUT...

SYSTEM TO PROFILE AND OPTIMIZE USER SOFTWARE IN A MANAGED RUN-TIME...

Apparatus, System, And Method For Persistent User-Level Thread

MECHANISM FOR INSTRUCTION SET BASED THREAD EXECUTION OF A PLURALITY...

CONTEXT STATE MANAGEMENT FOR PROCESSOR FEATURE SETS

INSTRUCTION SET ARCHITECTURE-BASED INTER-SEQUENCER COMMUNICATIONS W...

PRIMITIVES TO ENHANCE THREAD-LEVEL SPECULATION

MECHANISM FOR INSTRUCTION SET BASED THREAD EXECUTION ON A PLURALITY...

CONTEXT STATE MANAGEMENT FOR PROCESSOR FEATURE SETS

System To Profile And Optimize User Software In A Managed Run-Time...

PRIMITIVES TO ENHANCE THREAD-LEVEL SPECULATION

Mechanism for Monitoring Instruction Set Based Thread Execution on...

Apparatus, System, And Method For Persistent User-Level Thread

Providing a secure execution mode in a pre-boot environment

PRIMITIVES TO ENHANCE THREAD-LEVEL SPECULATION

MECHANISM TO HANDLE EVENTS IN A MACHINE WITH ISOLATED EXECUTION

MECHANISM TO HANDLE EVENTS IN A MACHINE WITH ISOLATED EXECUTION

MECHANISM TO HANDLE EVENTS IN A MACHINE WITH ISOLATED EXECUTION

Technique for context state management