Bulent Dervisoglu

Person

Mountain View, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
On-chip service processor
- Patent number 8,996,938
- Issue date Mar 31, 2015
- Intellectual Ventures I LLC
- Bulent Dervisoglu
- G01 - MEASURING TESTING
Information Patent Grant
On-chip service processor
- Patent number 8,239,716
- Issue date Aug 7, 2012
- Intellectual Ventures I LLC
- Bulent I. Dervisoglu
- G01 - MEASURING TESTING
Information Patent Grant
Variable clocked scan test improvements
- Patent number 7,890,899
- Issue date Feb 15, 2011
- Intellectual Ventures I LLC
- Laurence H. Cooke
- G01 - MEASURING TESTING
Information Patent Grant
On-chip service processor
- Patent number 7,836,371
- Issue date Nov 16, 2010
- Bulent Dervisoglu
- G01 - MEASURING TESTING
Information Patent Grant
Accelerated scan circuitry and method for reducing scan test data v...
- Patent number 7,752,515
- Issue date Jul 6, 2010
- Bulent I. Dervisoglu
- G01 - MEASURING TESTING
Information Patent Grant
Variable clocked scan test improvements
- Patent number 7,353,470
- Issue date Apr 1, 2008
- On-Chip Technologies, Inc.
- Laurence H. Cooke
- G01 - MEASURING TESTING
Information Patent Grant
Accelerated scan circuitry and method for reducing scan test data v...
- Patent number 7,200,784
- Issue date Apr 3, 2007
- On-Chip Technologies, Inc.
- Bulent Dervisoglu
- G01 - MEASURING TESTING
Information Patent Grant
Accelerated scan circuitry and method for reducing scan test data v...
- Patent number 7,197,681
- Issue date Mar 27, 2007
- On-Chip Technologies, Inc.
- Bulent Dervisoglu
- G01 - MEASURING TESTING
Information Patent Grant
Accelerated scan circuitry and method for reducing scan test data v...
- Patent number 7,188,286
- Issue date Mar 6, 2007
- On-Chip Technologies, Inc.
- Bulent Dervisoglu
- G01 - MEASURING TESTING
Information Patent Grant
Hierarchical test circuit structure for chips with multiple circuit...
- Patent number 7,181,705
- Issue date Feb 20, 2007
- Cadence Design Systems, Inc.
- Bulent Dervisoglu
- G01 - MEASURING TESTING
Information Patent Grant
On-chip service processor
- Patent number 7,080,301
- Issue date Jul 18, 2006
- On-Chip Technologies, Inc.
- Bulent Dervisoglu
- G01 - MEASURING TESTING
Information Patent Grant
On-chip service processor
- Patent number 6,964,001
- Issue date Nov 8, 2005
- On-Chip Technologies, Inc.
- Bulent Dervisoglu
- G01 - MEASURING TESTING
Information Patent Grant
Hierarchical test circuit structure for chips with multiple circuit...
- Patent number 6,886,121
- Issue date Apr 26, 2005
- Cadence Design Systems, Inc.
- Bulent Dervisoglu
- G01 - MEASURING TESTING
Information Patent Grant
Hierarchical test circuit structure for chips with multiple circuit...
- Patent number 6,816,996
- Issue date Nov 9, 2004
- Cadence Design Systems, Inc.
- Bulent Dervisoglu
Information Patent Grant
On-chip service processor for test and debug of integrated circuits
- Patent number 6,687,865
- Issue date Feb 3, 2004
- On-Chip Technologies, Inc.
- Bulent Dervisoglu
- G01 - MEASURING TESTING
Information Patent Grant
Hierarchical test circuit structure for chips with multiple circuit...
- Patent number 6,631,504
- Issue date Oct 7, 2003
- Cadence Design Systems, Inc.
- Bulent Dervisoglu
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for providing optimized access to circuits for...
- Patent number 6,594,802
- Issue date Jul 15, 2003
- Intellitech Corporation
- Michael Ricchetti
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
On-Chip Service Processor
- Publication number 20160011260
- Publication date Jan 14, 2016
- INTELLECTUAL VENTURES LLC
- Bulent DERVISOGLU
- G01 - MEASURING TESTING
Information Patent Application
ON-CHIP SERVICE PROCESSOR
- Publication number 20120011411
- Publication date Jan 12, 2012
- Intellectual Ventures I LLC
- Bulent Dervisoglu
- G01 - MEASURING TESTING
Information Patent Application
ON-CHIP SERVICE PROCESSOR
- Publication number 20100162046
- Publication date Jun 24, 2010
- OC Applications Research LLC
- Bulent Dervisoglu
- G01 - MEASURING TESTING
Information Patent Application
On-chip service processor
- Publication number 20080168309
- Publication date Jul 10, 2008
- On-Chip Technolgies, Inc.
- Bulent Dervisoglu
- G01 - MEASURING TESTING
Information Patent Application
Variable Clocked Scan Test Improvements
- Publication number 20080163020
- Publication date Jul 3, 2008
- ON-CHIP TECHNOLOGIES, INC.
- Laurence H. Cooke
- G01 - MEASURING TESTING
Information Patent Application
Accelerated Scan Circuitry and Method for Reducing Scan Test Data V...
- Publication number 20070162803
- Publication date Jul 12, 2007
- ON-CHIP TECHNOLOGIES, INC.
- Bulent Dervisoglu
- G01 - MEASURING TESTING
Information Patent Application
Variable clocked scan test improvements
- Publication number 20060195746
- Publication date Aug 31, 2006
- On-Chip Technologies, Inc.
- Laurence H. Cooke
- G01 - MEASURING TESTING
Information Patent Application
On-chip service processor
- Publication number 20060064615
- Publication date Mar 23, 2006
- On-Chip Technologies, Inc.
- Bulent Dervisoglu
- G01 - MEASURING TESTING
Information Patent Application
Accelerated scan circuitry and method for reducing scan test data v...
- Publication number 20050154948
- Publication date Jul 14, 2005
- On-Chip Technologies, Inc.
- Bulent Dervisoglu
- G01 - MEASURING TESTING
Information Patent Application
Accelerated scan circuitry and method for reducing scan test data v...
- Publication number 20050028060
- Publication date Feb 3, 2005
- On-Chip Technologies, Inc.
- Bulent Dervisoglu
- G01 - MEASURING TESTING
Information Patent Application
On-chip service processor
- Publication number 20040187054
- Publication date Sep 23, 2004
- On-Chip Technologies, Inc.
- Bulent Dervisoglu
- G01 - MEASURING TESTING
Information Patent Application
Accelerated scan circuitry and method for reducing scan test data v...
- Publication number 20040148554
- Publication date Jul 29, 2004
- On-Chip Technologies, Inc.
- Bulent Dervisoglu
- G01 - MEASURING TESTING
Information Patent Application
Hierarchical test circuit structure for chips with multiple circuit...
- Publication number 20030131327
- Publication date Jul 10, 2003
- Cadence Design Systems, Inc.
- Bulent Dervisoglu
- G01 - MEASURING TESTING
Information Patent Application
Hierarchical test circuit structure for chips with multiple circuit...
- Publication number 20020040458
- Publication date Apr 4, 2002
- Bulent Dervisoglu
- G01 - MEASURING TESTING
Information Patent Application
Hierarchical test circuit structure for chips with multiple circuit...
- Publication number 20020035442
- Publication date Mar 21, 2002
- Bulent Dervisoglu
- G01 - MEASURING TESTING

Bulent Dervisoglu

Person

Patents Grantslast 30 patents

On-chip service processor

On-chip service processor

Variable clocked scan test improvements

On-chip service processor

Accelerated scan circuitry and method for reducing scan test data v...

Variable clocked scan test improvements

Accelerated scan circuitry and method for reducing scan test data v...

Accelerated scan circuitry and method for reducing scan test data v...

Accelerated scan circuitry and method for reducing scan test data v...

Hierarchical test circuit structure for chips with multiple circuit...

On-chip service processor

On-chip service processor

Hierarchical test circuit structure for chips with multiple circuit...

Hierarchical test circuit structure for chips with multiple circuit...

On-chip service processor for test and debug of integrated circuits

Hierarchical test circuit structure for chips with multiple circuit...

Method and apparatus for providing optimized access to circuits for...

Patents Applicationslast 30 patents

On-Chip Service Processor

ON-CHIP SERVICE PROCESSOR

ON-CHIP SERVICE PROCESSOR

On-chip service processor

Variable Clocked Scan Test Improvements

Accelerated Scan Circuitry and Method for Reducing Scan Test Data V...

Variable clocked scan test improvements

On-chip service processor

Accelerated scan circuitry and method for reducing scan test data v...

Accelerated scan circuitry and method for reducing scan test data v...

On-chip service processor

Accelerated scan circuitry and method for reducing scan test data v...

Hierarchical test circuit structure for chips with multiple circuit...

Hierarchical test circuit structure for chips with multiple circuit...

Hierarchical test circuit structure for chips with multiple circuit...