Bupesh Pandita

Person

Raleigh, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Phase-locked-loop circuit employing a hybrid loop filter with sampl...
- Patent number 11,722,140
- Issue date Aug 8, 2023
- Microsoft Technology Licensing, LLC
- Ping Lu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable analog calibration circuit supporting iterative measur...
- Patent number 11,705,890
- Issue date Jul 18, 2023
- Microsoft Technology Licensing, LLC
- Anirban Banerjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Network transceiver with VGA channel specific equalization
- Patent number 11,658,696
- Issue date May 23, 2023
- Microsoft Technology Licensing, LLC
- Bupesh Pandita
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low-power, low-latency time-to-digital-converter-based serial link
- Patent number 10,965,442
- Issue date Mar 30, 2021
- QUALCOMM Incorporated
- Eskinder Hailu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
SerDes with adaptive clock data recovery
- Patent number 10,389,366
- Issue date Aug 20, 2019
- QUALCOMM Incorporated
- Eskinder Hailu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Delay locked loop (DLL) employing pulse to digital converter (PDC)...
- Patent number 9,998,126
- Issue date Jun 12, 2018
- QUALCOMM Incorporated
- Eskinder Hailu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Pulse to digital converter
- Patent number 9,971,312
- Issue date May 15, 2018
- QUALCOMM Incorporated
- Eskinder Hailu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Gate boosted low drop regulator
- Patent number 9,778,672
- Issue date Oct 3, 2017
- QUALCOMM Incorporated
- Zhuo Gao
- G05 - CONTROLLING REGULATING
Information Patent Grant
Apparatus and method for in situ analog signal diagnostic and debug...
- Patent number 9,729,163
- Issue date Aug 8, 2017
- QUALCOMM Incorporated
- Deqiang Song
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and method for combining currents from passive equalizer...
- Patent number 9,602,317
- Issue date Mar 21, 2017
- QUALCOMM Incorporated
- Eskinder Hailu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Fractional phase locked loop (PLL) architecture
- Patent number 9,577,646
- Issue date Feb 21, 2017
- QUALCOMM Incorporated
- Bupesh Pandita
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Linear equalizer with variable gain
- Patent number 9,520,872
- Issue date Dec 13, 2016
- QUALCOMM Incorporated
- Bupesh Pandita
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Phase locked loop (PLL) architecture
- Patent number 9,485,085
- Issue date Nov 1, 2016
- QUALCOMM Incorporated
- Kenneth Luis Arcudia
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
ADAPTIVE CHANNEL EQUALIZATION FOR A DUO-BINARY TRANSCEIVER
- Publication number 20240333563
- Publication date Oct 3, 2024
- Microsoft Technology Licensing, LLC
- Bupesh PANDITA
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PHASE-LOCKED LOOPS (PLL) INCLUDING DIGITALLY CONTROLLED OSCILLATOR...
- Publication number 20240267052
- Publication date Aug 8, 2024
- Microsoft Technology Licensing, LLC
- Ping LU
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
NETWORK TRANSCEIVER WITH VGA CHANNEL SPECIFIC EQUALIZATION
- Publication number 20230261688
- Publication date Aug 17, 2023
- Microsoft Technology Licensing, LLC
- Bupesh PANDITA
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PHASE-LOCKED-LOOP CIRCUIT EMPLOYING A HYBRID LOOP FILTER WITH SAMPL...
- Publication number 20230216509
- Publication date Jul 6, 2023
- Microsoft Technology Licensing, LLC
- Ping LU
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PROGRAMMABLE ANALOG CALIBRATION CIRCUIT SUPPORTING ITERATIVE MEASUR...
- Publication number 20230060647
- Publication date Mar 2, 2023
- Microsoft Technology Licensing, LLC
- Anirban BANERJEE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NETWORK TRANSCEIVER WITH VGA CHANNEL SPECIFIC EQUALIZATION
- Publication number 20220302951
- Publication date Sep 22, 2022
- Microsoft Technology Licensing, LLC
- Bupesh PANDITA
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOW-POWER, LOW-LATENCY TIME-TO-DIGITAL-CONVERTER-BASED SERIAL LINK
- Publication number 20200106597
- Publication date Apr 2, 2020
- QUALCOMM Incorporated
- Eskinder Hailu
- G04 - HOROLOGY
Information Patent Application
SERDES WITH ADAPTIVE CLOCK DATA RECOVERY
- Publication number 20190007053
- Publication date Jan 3, 2019
- QUALCOMM Incorporated
- Eskinder Hailu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
GATE BOOSTED LOW DROP REGULATOR
- Publication number 20170285675
- Publication date Oct 5, 2017
- QUALCOMM Incorporated
- Zhuo Gao
- G05 - CONTROLLING REGULATING
Information Patent Application
APPARATUS AND METHOD FOR COMBINING CURRENTS FROM PASSIVE EQUALIZER...
- Publication number 20170104616
- Publication date Apr 13, 2017
- QUALCOMM Incorporated
- Eskinder Hailu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
NEW FRACTIONAL PHASE LOCKED LOOP (PLL) ARCHITECTURE
- Publication number 20170041005
- Publication date Feb 9, 2017
- QUALCOMM Incorporated
- Bupesh Pandita
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
NOVEL PHASE LOCKED LOOP (PLL) ARCHITECTURE
- Publication number 20160269172
- Publication date Sep 15, 2016
- Qualcomm, Incorporated.
- Kenneth Luis Arcudia
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
BUILT-IN TEST STRUCTURE FOR A RECEIVER
- Publication number 20160216317
- Publication date Jul 28, 2016
- Qualcomm, Incorporated.
- Minhan Chen
- G01 - MEASURING TESTING
Information Patent Application
LINEAR EQUALIZER WITH VARIABLE GAIN
- Publication number 20160182038
- Publication date Jun 23, 2016
- QUALCOMM Incorporated
- Bupesh Pandita
- H03 - BASIC ELECTRONIC CIRCUITRY

Bupesh Pandita

Person

Patents Grantslast 30 patents

Phase-locked-loop circuit employing a hybrid loop filter with sampl...

Programmable analog calibration circuit supporting iterative measur...

Network transceiver with VGA channel specific equalization

Low-power, low-latency time-to-digital-converter-based serial link

SerDes with adaptive clock data recovery

Delay locked loop (DLL) employing pulse to digital converter (PDC)...

Pulse to digital converter

Gate boosted low drop regulator

Apparatus and method for in situ analog signal diagnostic and debug...

Apparatus and method for combining currents from passive equalizer...

Fractional phase locked loop (PLL) architecture

Linear equalizer with variable gain

Phase locked loop (PLL) architecture

Patents Applicationslast 30 patents

ADAPTIVE CHANNEL EQUALIZATION FOR A DUO-BINARY TRANSCEIVER

PHASE-LOCKED LOOPS (PLL) INCLUDING DIGITALLY CONTROLLED OSCILLATOR...

NETWORK TRANSCEIVER WITH VGA CHANNEL SPECIFIC EQUALIZATION

PHASE-LOCKED-LOOP CIRCUIT EMPLOYING A HYBRID LOOP FILTER WITH SAMPL...

PROGRAMMABLE ANALOG CALIBRATION CIRCUIT SUPPORTING ITERATIVE MEASUR...

NETWORK TRANSCEIVER WITH VGA CHANNEL SPECIFIC EQUALIZATION

LOW-POWER, LOW-LATENCY TIME-TO-DIGITAL-CONVERTER-BASED SERIAL LINK

SERDES WITH ADAPTIVE CLOCK DATA RECOVERY

GATE BOOSTED LOW DROP REGULATOR

APPARATUS AND METHOD FOR COMBINING CURRENTS FROM PASSIVE EQUALIZER...

NEW FRACTIONAL PHASE LOCKED LOOP (PLL) ARCHITECTURE

NOVEL PHASE LOCKED LOOP (PLL) ARCHITECTURE

BUILT-IN TEST STRUCTURE FOR A RECEIVER

LINEAR EQUALIZER WITH VARIABLE GAIN