Byoung Jin CHOI

Person

Kanata, CA

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for connecting memory dies to form a memory sy...
- Patent number 9,159,647
- Issue date Oct 13, 2015
- NovaChips Canada Inc.
- Byoung Jin Choi
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system and method using stacked memory device dice
- Patent number 9,123,394
- Issue date Sep 1, 2015
- Conversant Intellectual Property Management Inc.
- Byoung Jin Choi
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system and method using stacked memory device dice
- Patent number 8,879,296
- Issue date Nov 4, 2014
- Conversant Intellectual Property Management Inc.
- Byoung Jin Choi
- G11 - INFORMATION STORAGE
Information Patent Grant
Reduced noise DRAM sensing
- Patent number 8,824,231
- Issue date Sep 2, 2014
- Conversant Intellectual Property Management Inc.
- Byoung Jin Choi
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device with sense amplifier and bitline isolation
- Patent number 8,780,664
- Issue date Jul 15, 2014
- Conversant Intellectual Property Management Inc.
- Byoung Jin Choi
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device with sense amplifier and bitline isolation
- Patent number 8,462,573
- Issue date Jun 11, 2013
- Mosaid Technolgies Incorporated
- Byoung Jin Choi
- G11 - INFORMATION STORAGE
Information Patent Grant
High-speed interface for daisy-chained devices
- Patent number 8,463,959
- Issue date Jun 11, 2013
- MOSAID Technologies Incorporated
- Byoung Jin Choi
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE
- Publication number 20160071825
- Publication date Mar 10, 2016
- Conversant Intellectual Property Management Inc.
- Byoung Jin CHOI
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE
- Publication number 20150036408
- Publication date Feb 5, 2015
- Conversant Intellectual Property Management Inc.
- Byoung Jin CHOI
- G11 - INFORMATION STORAGE
Information Patent Application
HIGH SPEED INTERFACE FOR DAISY-CHAINED DEVICES
- Publication number 20130275628
- Publication date Oct 17, 2013
- Byoung Jin CHOI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR MEMORY DEVICE WITH SENSE AMPLIFIER AND BITLINE ISOLATION
- Publication number 20130265839
- Publication date Oct 10, 2013
- Byoung Jin CHOI
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR CONNECTING MEMORY DIES TO FORM A MEMORY SY...
- Publication number 20130193582
- Publication date Aug 1, 2013
- MOSAID TECHNOLOGIES INCORPORATED
- Byoung Jin CHOI
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE
- Publication number 20130135917
- Publication date May 30, 2013
- MOSAID TECHNOLOGIES INCORPORATED
- Byoung Jin CHOI
- G11 - INFORMATION STORAGE
Information Patent Application
REDUCED NOISE DRAM SENSING
- Publication number 20130083615
- Publication date Apr 4, 2013
- MOSAID TECHNOLOGIES INCORPORATED
- Byoung Jin CHOI
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY DEVICE WITH SENSE AMPLIFIER AND BITLINE ISOLATION
- Publication number 20110305098
- Publication date Dec 15, 2011
- Byoung Jin CHOI
- G11 - INFORMATION STORAGE
Information Patent Application
HIGH-SPEED INTERFACE FOR DAISY-CHAINED DEVICES
- Publication number 20110296056
- Publication date Dec 1, 2011
- MOSAID TECHNOLOGIES INCORPORATED
- Byoung Jin Choi
- G06 - COMPUTING CALCULATING COUNTING

Byoung Jin CHOI

Person

Patents Grantslast 30 patents

Method and apparatus for connecting memory dies to form a memory sy...

Memory system and method using stacked memory device dice

Memory system and method using stacked memory device dice

Reduced noise DRAM sensing

Semiconductor memory device with sense amplifier and bitline isolation

Semiconductor memory device with sense amplifier and bitline isolation

High-speed interface for daisy-chained devices

Patents Applicationslast 30 patents

MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE

MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE

HIGH SPEED INTERFACE FOR DAISY-CHAINED DEVICES

SEMICONDUCTOR MEMORY DEVICE WITH SENSE AMPLIFIER AND BITLINE ISOLATION

METHOD AND APPARATUS FOR CONNECTING MEMORY DIES TO FORM A MEMORY SY...

MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE

REDUCED NOISE DRAM SENSING

SEMICONDUCTOR MEMORY DEVICE WITH SENSE AMPLIFIER AND BITLINE ISOLATION

HIGH-SPEED INTERFACE FOR DAISY-CHAINED DEVICES