Byung Tai Do

Person

Singapore, SG

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor device and method of forming interposer frame over se...
- Patent number RE48408
- Issue date Jan 26, 2021
- JCET Semiconductor (Shaoxing) Co., Ltd.
- Reza A. Pagaila
Information Patent Grant
Semiconductor device and method of forming interposer frame over se...
- Patent number RE48111
- Issue date Jul 21, 2020
- JCET Semiconductor (Shaoxing) Co. Ltd.
- Reza A. Pagaila
Information Patent Grant
Semiconductor device and method of forming Fo-WLCSP with recessed i...
- Patent number 10,388,584
- Issue date Aug 20, 2019
- STATS ChipPAC Pte. Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system with substrate and method of ma...
- Patent number 10,109,587
- Issue date Oct 23, 2018
- STATS ChipPAC Pte. Ltd.
- Dao Nguyen Phu Cuong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming a package in-fan out pac...
- Patent number 10,068,862
- Issue date Sep 4, 2018
- STATS ChipPAC Pte. Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system and method of manufacture thereof
- Patent number 10,043,733
- Issue date Aug 7, 2018
- STATS ChipPAC Pte. Ltd.
- Reza Argenty Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming interposer frame over se...
- Patent number 9,893,045
- Issue date Feb 13, 2018
- STATS ChipPAC Pte. Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package-on-package using through-hole via die on saw streets
- Patent number 9,847,253
- Issue date Dec 19, 2017
- STATS ChipPAC Pte. Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming stepped interconnect lay...
- Patent number 9,824,975
- Issue date Nov 21, 2017
- STATS ChipPAC Pte. Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system with a grid array with a leadfr...
- Patent number 9,799,589
- Issue date Oct 24, 2017
- STATS ChipPAC Pte. Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming cavity adjacent to sensi...
- Patent number 9,679,881
- Issue date Jun 13, 2017
- STATS ChipPAC Pte. Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of providing z-interconnect conduct...
- Patent number 9,640,504
- Issue date May 2, 2017
- STATS ChipPAC Pte. Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system with unplated leadframe and met...
- Patent number 9,620,480
- Issue date Apr 11, 2017
- STATS ChipPAC Pte. Ltd.
- Garret Dimaculangan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming conductive vias with tre...
- Patent number 9,601,369
- Issue date Mar 21, 2017
- STATS ChipPAC Pte. Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming a shielding layer betwee...
- Patent number 9,583,446
- Issue date Feb 28, 2017
- STATS ChipPAC Pte. Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system with routable trace and method...
- Patent number 9,576,873
- Issue date Feb 21, 2017
- STATS ChipPAC Pte. Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming interconnect structure a...
- Patent number 9,530,738
- Issue date Dec 27, 2016
- STATS ChipPAC Pte. Ltd.
- Linda Pei Ee Chua
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package-in-package using through-hole via die on saw streets
- Patent number 9,524,938
- Issue date Dec 20, 2016
- STATS ChipPAC Pte. Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming base substrate with rece...
- Patent number 9,449,932
- Issue date Sep 20, 2016
- STATS ChipPAC Pte. Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of embedding thermally conductive l...
- Patent number 9,443,828
- Issue date Sep 13, 2016
- STATS ChipPAC Pte. Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming penetrable film encapsul...
- Patent number 9,431,331
- Issue date Aug 30, 2016
- STATS ChipPAC Pte. Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming B-stage conductive polym...
- Patent number 9,418,941
- Issue date Aug 16, 2016
- STATS ChipPAC Pte. Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system with substrate and method of ma...
- Patent number 9,412,624
- Issue date Aug 9, 2016
- STATS ChipPAC Pte. Ltd.
- Dao Nguyen Phu Cuong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Extended redistribution layers bumped wafer
- Patent number 9,406,647
- Issue date Aug 2, 2016
- STATS ChipPAC Pte. Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device including pre-fabricated shielding frame dispo...
- Patent number 9,406,619
- Issue date Aug 2, 2016
- STATS ChipPAC Pte. Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of using substrate with conductive...
- Patent number 9,368,423
- Issue date Jun 14, 2016
- STATS ChipPAC Pte. Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming double-sided through via...
- Patent number 9,343,429
- Issue date May 17, 2016
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming through vias with reflow...
- Patent number 9,331,002
- Issue date May 3, 2016
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system with transferable trace lead frame
- Patent number 9,324,584
- Issue date Apr 26, 2016
- Stats Chippac Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system with external interconnect and...
- Patent number 9,324,641
- Issue date Apr 26, 2016
- Stats Chippac Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Semiconductor Device and Method of Forming Interconnect Structure a...
- Publication number 20170062390
- Publication date Mar 2, 2017
- STATS ChipPAC Pte Ltd.
- Linda Pei Ee Chua
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming a Package In-Fan Out Pac...
- Publication number 20160300817
- Publication date Oct 13, 2016
- STATS ChipPAC, Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE MECHANI...
- Publication number 20160190056
- Publication date Jun 30, 2016
- SooSan Park
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Interposer Frame Over Se...
- Publication number 20160111410
- Publication date Apr 21, 2016
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Substrate Having Conduct...
- Publication number 20150279815
- Publication date Oct 1, 2015
- STATS ChipPAC, Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Embedding Thermally Conductive L...
- Publication number 20150228628
- Publication date Aug 13, 2015
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VIALESS SUBSTRATE AND METH...
- Publication number 20150179555
- Publication date Jun 25, 2015
- Sung Soo Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Stepped Interconnect Lay...
- Publication number 20150145128
- Publication date May 28, 2015
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming a Shielding Layer Betwee...
- Publication number 20150115394
- Publication date Apr 30, 2015
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SIDE SOLDERABLE LEADS AND...
- Publication number 20150084172
- Publication date Mar 26, 2015
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Using Substrate With Conductive...
- Publication number 20150001707
- Publication date Jan 1, 2015
- STATS ChipPAC, Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Interconnect Structure a...
- Publication number 20140353846
- Publication date Dec 4, 2014
- STATS ChipPAC, Ltd.
- Linda Pei Ee Chua
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CORELESS INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACT...
- Publication number 20140284791
- Publication date Sep 25, 2014
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Conductive Vias with Tre...
- Publication number 20140217609
- Publication date Aug 7, 2014
- STATS ChipPAC, Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Providing Z-Interconnect Conduct...
- Publication number 20140203443
- Publication date Jul 24, 2014
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Extended Redistribution Layers Bumped Wafer
- Publication number 20140197540
- Publication date Jul 17, 2014
- STATS ChipPAC, Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOLDED GRID-ARRAY MECHANIS...
- Publication number 20140197548
- Publication date Jul 17, 2014
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TRANSFERABLE TRACE LEAD FRAME
- Publication number 20140167236
- Publication date Jun 19, 2014
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTABLE GRID ARRAY LEAD F...
- Publication number 20140165389
- Publication date Jun 19, 2014
- Byung Tai DO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH GRID-ARRAY MECHANISM AND M...
- Publication number 20140008774
- Publication date Jan 9, 2014
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Cavity Adjacent to Sensi...
- Publication number 20140008769
- Publication date Jan 9, 2014
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Embedding Thermally Conductive L...
- Publication number 20140001627
- Publication date Jan 2, 2014
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Penetrable Film Encapsul...
- Publication number 20130299971
- Publication date Nov 14, 2013
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Through Vias with Reflow...
- Publication number 20130299975
- Publication date Nov 14, 2013
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Interconnect Structure a...
- Publication number 20130292850
- Publication date Nov 7, 2013
- Linda Pei Ee Chua
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTABLE CIRCUITRY AND MET...
- Publication number 20130256861
- Publication date Oct 3, 2013
- STATS ChipPAC Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A GRID ARRAY WITH A LEADFR...
- Publication number 20130249118
- Publication date Sep 26, 2013
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EXTERNAL INTERCONNECT AND...
- Publication number 20130249068
- Publication date Sep 26, 2013
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND LEADFRAM...
- Publication number 20130249065
- Publication date Sep 26, 2013
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TERMINALS AND METHOD OF MA...
- Publication number 20130249077
- Publication date Sep 26, 2013
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS

Byung Tai Do

Person

Patents Grantslast 30 patents

Semiconductor device and method of forming interposer frame over se...

Semiconductor device and method of forming interposer frame over se...

Semiconductor device and method of forming Fo-WLCSP with recessed i...

Integrated circuit packaging system with substrate and method of ma...

Semiconductor device and method of forming a package in-fan out pac...

Integrated circuit packaging system and method of manufacture thereof

Semiconductor device and method of forming interposer frame over se...

Package-on-package using through-hole via die on saw streets

Semiconductor device and method of forming stepped interconnect lay...

Integrated circuit packaging system with a grid array with a leadfr...

Semiconductor device and method of forming cavity adjacent to sensi...

Semiconductor device and method of providing z-interconnect conduct...

Integrated circuit packaging system with unplated leadframe and met...

Semiconductor device and method of forming conductive vias with tre...

Semiconductor device and method of forming a shielding layer betwee...

Integrated circuit packaging system with routable trace and method...

Semiconductor device and method of forming interconnect structure a...

Package-in-package using through-hole via die on saw streets

Semiconductor device and method of forming base substrate with rece...

Semiconductor device and method of embedding thermally conductive l...

Semiconductor device and method of forming penetrable film encapsul...

Semiconductor device and method of forming B-stage conductive polym...

Integrated circuit packaging system with substrate and method of ma...

Extended redistribution layers bumped wafer

Semiconductor device including pre-fabricated shielding frame dispo...

Semiconductor device and method of using substrate with conductive...

Semiconductor device and method of forming double-sided through via...

Semiconductor device and method of forming through vias with reflow...

Integrated circuit packaging system with transferable trace lead frame

Integrated circuit packaging system with external interconnect and...

Patents Applicationslast 30 patents

Semiconductor Device and Method of Forming Interconnect Structure a...

Semiconductor Device and Method of Forming a Package In-Fan Out Pac...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE MECHANI...

Semiconductor Device and Method of Forming Interposer Frame Over Se...

Semiconductor Device and Method of Forming Substrate Having Conduct...

Semiconductor Device and Method of Embedding Thermally Conductive L...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VIALESS SUBSTRATE AND METH...

Semiconductor Device and Method of Forming Stepped Interconnect Lay...

Semiconductor Device and Method of Forming a Shielding Layer Betwee...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SIDE SOLDERABLE LEADS AND...

Semiconductor Device and Method of Using Substrate With Conductive...

Semiconductor Device and Method of Forming Interconnect Structure a...

CORELESS INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACT...

Semiconductor Device and Method of Forming Conductive Vias with Tre...

Semiconductor Device and Method of Providing Z-Interconnect Conduct...

Extended Redistribution Layers Bumped Wafer

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOLDED GRID-ARRAY MECHANIS...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TRANSFERABLE TRACE LEAD FRAME

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTABLE GRID ARRAY LEAD F...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH GRID-ARRAY MECHANISM AND M...

Semiconductor Device and Method of Forming Cavity Adjacent to Sensi...

Semiconductor Device and Method of Embedding Thermally Conductive L...

Semiconductor Device and Method of Forming Penetrable Film Encapsul...

Semiconductor Device and Method of Forming Through Vias with Reflow...

Semiconductor Device and Method of Forming Interconnect Structure a...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTABLE CIRCUITRY AND MET...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A GRID ARRAY WITH A LEADFR...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EXTERNAL INTERCONNECT AND...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND LEADFRAM...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TERMINALS AND METHOD OF MA...