Camille C. Raad

Person

Folsom, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Techniques for handling errors in persistent memory
- Patent number 11,119,838
- Issue date Sep 14, 2021
- Intel Corporation
- Mohan J. Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technologies for contemporaneous access of non-volatile and volatil...
- Patent number 10,915,254
- Issue date Feb 9, 2021
- Intel Corporation
- Kunal A. Khochare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for implementing a multi-level memory hierarchy
- Patent number 10,719,443
- Issue date Jul 21, 2020
- Intel Corporation
- Raj K. Ramanujan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for handling errors in persistent memory
- Patent number 10,417,070
- Issue date Sep 17, 2019
- Intel Corporation
- Mohan J. Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technologies for contemporaneous access of non-volatile and volatil...
- Patent number 10,296,238
- Issue date May 21, 2019
- Intel Corporation
- Kunal A. Khochare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for implementing a multi-level memory hierarchy
- Patent number 10,241,912
- Issue date Mar 26, 2019
- Intel Corporation
- Raj K. Ramanujan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clearing poison status on read accesses to volatile memory regions...
- Patent number 9,817,738
- Issue date Nov 14, 2017
- Intel Corporation
- Raj K. Ramanujan
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for handling errors in persistent memory
- Patent number 9,753,793
- Issue date Sep 5, 2017
- Intel Corporation
- Mohan J. Kumar
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for implementing a multi-level memory hierarchy
- Patent number 9,600,416
- Issue date Mar 21, 2017
- Intel Corporation
- Raj K. Ramanujan
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
TECHNIQUES FOR HANDLING ERRORS IN PERSISTENT MEMORY
- Publication number 20200117526
- Publication date Apr 16, 2020
- Intel Corporation
- Mohan J. Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGIES FOR CONTEMPORANEOUS ACCESS OF NON-VOLATILE AND VOLATIL...
- Publication number 20190258414
- Publication date Aug 22, 2019
- Intel Corporation
- Kunal A. Khochare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY
- Publication number 20190220406
- Publication date Jul 18, 2019
- Intel Corporation
- Raj K. RAMANUJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techniques for Handling Errors in Persistent Memory
- Publication number 20180039528
- Publication date Feb 8, 2018
- Intel Corporation
- Mohan J. Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY
- Publication number 20170249250
- Publication date Aug 31, 2017
- Intel Corporation
- Raj K. RAMANUJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGIES FOR CONTEMPORANEOUS ACCESS OF NON-VOLATILE AND VOLATIL...
- Publication number 20170177244
- Publication date Jun 22, 2017
- Kunal A. Khochare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLEARING POISON STATUS ON READ ACCESSES TO VOLATILE MEMORY REGIONS...
- Publication number 20170068537
- Publication date Mar 9, 2017
- Intel Corporation
- Raj K. Ramanujan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techniques for Handling Errors in Persistent Memory
- Publication number 20150378808
- Publication date Dec 31, 2015
- Mohan J. Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY
- Publication number 20140129767
- Publication date May 8, 2014
- Raj K Ramanujan
- G06 - COMPUTING CALCULATING COUNTING

Camille C. Raad

Person

Patents Grantslast 30 patents

Techniques for handling errors in persistent memory

Technologies for contemporaneous access of non-volatile and volatil...

Apparatus and method for implementing a multi-level memory hierarchy

Techniques for handling errors in persistent memory

Technologies for contemporaneous access of non-volatile and volatil...

Apparatus and method for implementing a multi-level memory hierarchy

Clearing poison status on read accesses to volatile memory regions...

Techniques for handling errors in persistent memory

Apparatus and method for implementing a multi-level memory hierarchy

Patents Applicationslast 30 patents

TECHNIQUES FOR HANDLING ERRORS IN PERSISTENT MEMORY

TECHNOLOGIES FOR CONTEMPORANEOUS ACCESS OF NON-VOLATILE AND VOLATIL...

APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY

Techniques for Handling Errors in Persistent Memory

APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY

TECHNOLOGIES FOR CONTEMPORANEOUS ACCESS OF NON-VOLATILE AND VOLATIL...

CLEARING POISON STATUS ON READ ACCESSES TO VOLATILE MEMORY REGIONS...

Techniques for Handling Errors in Persistent Memory

APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY