Carlos A. Lizalde Moreno

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Guadalajara, MX

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Patents Grantslast 30 patents

Information Patent Grant
High speed differential pinout arrangement including a power pin
- Patent number 11,990,709
- Issue date May 21, 2024
- Intel Corporation
- Raul Enriquez Shibayama
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Crosstalk reduction in signal lines by crosstalk introduction
- Patent number 9,337,521
- Issue date May 10, 2016
- Intel Corporation
- Raul Enriquez Shibayama
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
HIGH SPEED DIFFERENTIAL PINOUT ARRANGEMENT INCLUDING A POWER PIN
- Publication number 20210391671
- Publication date Dec 16, 2021
- Intel Corporation
- Raul Enriquez Shibayama
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRICAL ROUTING COMPONENT LAYOUT FOR CROSSTALK REDUCTION
- Publication number 20200083155
- Publication date Mar 12, 2020
- Intel Corporation
- Raul ENRIQUEZ SHIBAYAMA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIFFERENTIAL VIA WITH PER-LAYER VOID
- Publication number 20190116668
- Publication date Apr 18, 2019
- Intel Corporation
- Carlos Alberto Lizalde Moreno
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CROSSTALK REDUCTION IN SIGNAL LINES BY CROSSTALK INTRODUCTION
- Publication number 20150130553
- Publication date May 14, 2015
- Raul Enriquez Shibayama
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Reducing Far End Crosstalk in Single Ended Interconnects and Buses
- Publication number 20150085458
- Publication date Mar 26, 2015
- Raul Enriquez Shibayama
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR