Cesar Payan

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San Jose, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Lot-optimized wafer level burn-in
- Patent number 6,800,495
- Issue date Oct 5, 2004
- Cypress Semiconductor Corporation
- Cesar Payan
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
Lot-optimized wafer level burn-in
- Publication number 20040058461
- Publication date Mar 25, 2004
- Cesar Payan
- G01 - MEASURING TESTING