Chad D. Hancock

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Hillsboro, OR, US

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Patents Grantslast 30 patents

Information Patent Grant
Reducing power consumption in a fused multiply-add (FMA) unit of a...
- Patent number 9,778,911
- Issue date Oct 3, 2017
- Intel Corporation
- Chad D. Hancock
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing power consumption in a fused multiply-add (FMA) unit of a...
- Patent number 9,360,920
- Issue date Jun 7, 2016
- Intel Corporation
- Chad D. Hancock
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...

Patents Applicationslast 30 patents

Information Patent Application
REDUCING POWER CONSUMPTION IN A FUSED MULTIPLY-ADD (FMA) UNIT OF A...
- Publication number 20160321031
- Publication date Nov 3, 2016
- Intel Corporation
- Chad D. Hancock
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR VECTOR COMPUTE AND ACCUMULATE
- Publication number 20140108480
- Publication date Apr 17, 2014
- Elmoustapha Ould-Ahmed-Vall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LATER STAGE READ PORT REDUCTION
- Publication number 20130339689
- Publication date Dec 19, 2013
- Srikanth T. Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCING POWER CONSUMPTION IN A FUSED MULTIPLY-ADD (FMA) UNIT OF A...
- Publication number 20130268794
- Publication date Oct 10, 2013
- Chad D. Hancock
- G06 - COMPUTING CALCULATING COUNTING