Chaithanya Dudha

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Circuit architecture for determining threshold ranges and values of...
- Patent number 11,842,168
- Issue date Dec 12, 2023
- Xilinx, Inc.
- Sai Lalith Chaitanya Ambatipudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implementing a hardware description language memory using heterogen...
- Patent number 11,429,769
- Issue date Aug 30, 2022
- Xilinx, Inc.
- Pradip Kar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-chip memory access pattern detection for power and resource redu...
- Patent number 11,188,697
- Issue date Nov 30, 2021
- Xilinx, Inc.
- Chaithanya Dudha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi dimensional memory compression using bytewide write enable
- Patent number 11,100,267
- Issue date Aug 24, 2021
- Xilinx, Inc.
- Nithin Kumar Guggilla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implementing a circuit design with re-convergence
- Patent number 10,990,736
- Issue date Apr 27, 2021
- Xilinx, Inc.
- Chaithanya Dudha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems for optimization of read-only memory (ROM)
- Patent number 10,726,175
- Issue date Jul 28, 2020
- Xilinx, Inc.
- Chaithanya Dudha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Local retiming optimization for circuit designs
- Patent number 10,678,983
- Issue date Jun 9, 2020
- Xilinx, Inc.
- Shangzhi Sun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register pull-out for sequential circuit blocks in circuit designs
- Patent number 10,642,951
- Issue date May 5, 2020
- Xilinx, Inc.
- Govinda Keshavdas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verifying equivalence of design latency
- Patent number 10,606,979
- Issue date Mar 31, 2020
- Xilinx, Inc.
- Shangzhi Sun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for enhancing performance by moving or adding...
- Patent number 10,430,539
- Issue date Oct 1, 2019
- Xilinx, Inc.
- Chaithanya Dudha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic power reduction in circuit designs and circuits
- Patent number 10,387,600
- Issue date Aug 20, 2019
- Xilinx, Inc.
- Chaithanya Dudha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Partitioning memory blocks for reducing dynamic power consumption
- Patent number 10,366,001
- Issue date Jul 30, 2019
- Xilinx, Inc.
- Nithin Kumar Guggilla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit design transformation for automatic latency reduction
- Patent number 10,289,786
- Issue date May 14, 2019
- Xilinx, Inc.
- Chaithanya Dudha
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SMART PREDICTOR CIRCUITRY INSERTION BASED ON STRUCTURAL ANALYSIS AN...
- Publication number 20250005249
- Publication date Jan 2, 2025
- Xilinx, Inc.
- Fan Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RETIMING SEQUENTIAL ELEMENTS HAVING INITITAL STATES
- Publication number 20240256749
- Publication date Aug 1, 2024
- Xilinx, Inc.
- Chaithanya Dudha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE NON-LINEAR ACTIVATION ENGINE FOR NEURAL NETWORK ACCELE...
- Publication number 20230297824
- Publication date Sep 21, 2023
- Xilinx, Inc.
- Rajeev Patwari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT ARCHITECTURE FOR DETERMINING THRESHOLD RANGES AND VALUES OF...
- Publication number 20230096400
- Publication date Mar 30, 2023
- Xilinx, Inc.
- Sai Lalith Chaitanya Ambatipudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BEHAVIORAL-LEVEL TIMING AND AREA OPTIMIATION
- Publication number 20220261523
- Publication date Aug 18, 2022
- Xilinx, Inc.
- FAN ZHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC POWER REDUCTION IN CIRCUIT DESIGNS AND CIRCUITS
- Publication number 20180075172
- Publication date Mar 15, 2018
- Xilinx, Inc.
- Chaithanya Dudha
- G06 - COMPUTING CALCULATING COUNTING

Chaithanya Dudha

Person

Patents Grantslast 30 patents

Circuit architecture for determining threshold ranges and values of...

Implementing a hardware description language memory using heterogen...

On-chip memory access pattern detection for power and resource redu...

Multi dimensional memory compression using bytewide write enable

Implementing a circuit design with re-convergence

Systems for optimization of read-only memory (ROM)

Local retiming optimization for circuit designs

Register pull-out for sequential circuit blocks in circuit designs

Verifying equivalence of design latency

Method and apparatus for enhancing performance by moving or adding...

Dynamic power reduction in circuit designs and circuits

Partitioning memory blocks for reducing dynamic power consumption

Circuit design transformation for automatic latency reduction

Patents Applicationslast 30 patents

SMART PREDICTOR CIRCUITRY INSERTION BASED ON STRUCTURAL ANALYSIS AN...

RETIMING SEQUENTIAL ELEMENTS HAVING INITITAL STATES

PROGRAMMABLE NON-LINEAR ACTIVATION ENGINE FOR NEURAL NETWORK ACCELE...

CIRCUIT ARCHITECTURE FOR DETERMINING THRESHOLD RANGES AND VALUES OF...

BEHAVIORAL-LEVEL TIMING AND AREA OPTIMIATION

DYNAMIC POWER REDUCTION IN CIRCUIT DESIGNS AND CIRCUITS