Chakrapani Pathikonda

Person

Beaverton, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Core clock correction in a 2/n mode clocking scheme
- Patent number 6,268,749
- Issue date Jul 31, 2001
- Intel Corporation
- Matthew A. Fisch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Core clock correction in a 2/N mode clocking scheme
- Patent number 6,208,180
- Issue date Mar 27, 2001
- Intel Corporation
- Matthew A. Fisch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for generating bus clock signals with a 1/N characteristi...
- Patent number 6,114,887
- Issue date Sep 5, 2000
- Intel Corporation
- Chakrapani Pathikonda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for generating 2/N mode bus clock signals
- Patent number 6,104,219
- Issue date Aug 15, 2000
- Intel Corporation
- Javed S. Barkatullah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Auto-configuration support for multiple processor-ready pair or FRC...
- Patent number 6,061,599
- Issue date May 9, 2000
- Intel Corporation
- Michael W. Rhodehamel
- G05 - CONTROLLING REGULATING
Information Patent Grant
Pad cells for a 2/N mode clocking scheme
- Patent number 5,862,373
- Issue date Jan 19, 1999
- Intel Corporation
- Chakrapani Pathikonda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Core clock correction in a 2/N mode clocking scheme
- Patent number 5,834,956
- Issue date Nov 10, 1998
- Intel Corporation
- Chakrapani Pathikonda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for preventing logic glitches in a 2/n clockin...
- Patent number 5,826,067
- Issue date Oct 20, 1998
- Intel Corporation
- Matthew A. Fisch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for generating 2/N mode bus clock signals
- Patent number 5,821,784
- Issue date Oct 13, 1998
- Intel Corporation
- Javed S. Barkatullah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for generating bus clock signals with a 1/N characteristi...
- Patent number 5,802,132
- Issue date Sep 1, 1998
- Intel Corporation
- Chakrapani Pathikonda
- G06 - COMPUTING CALCULATING COUNTING

Chakrapani Pathikonda

Person

Patents Grantslast 30 patents

Core clock correction in a 2/n mode clocking scheme

Core clock correction in a 2/N mode clocking scheme

Apparatus for generating bus clock signals with a 1/N characteristi...

Method and apparatus for generating 2/N mode bus clock signals

Auto-configuration support for multiple processor-ready pair or FRC...

Pad cells for a 2/N mode clocking scheme

Core clock correction in a 2/N mode clocking scheme

Method and apparatus for preventing logic glitches in a 2/n clockin...

Method and apparatus for generating 2/N mode bus clock signals

Apparatus for generating bus clock signals with a 1/N characteristi...