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Chan-Chi J. Cheng
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San Jose, CA, US
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Patents Grants
last 30 patents
Information
Patent Grant
Testing of soft error detection logic for programmable logic devices
Patent number
8,370,691
Issue date
Feb 5, 2013
Lattice Semiconductor Corporation
Chan-Chi Jason Cheng
G11 - INFORMATION STORAGE
Information
Patent Grant
Soft error detection logic testing systems and methods
Patent number
8,065,574
Issue date
Nov 22, 2011
Lattice Semiconductor Corporation
Chan-Chi Jason Cheng
G11 - INFORMATION STORAGE
Information
Patent Grant
Compression and decompression of configuration data using repeated...
Patent number
7,902,865
Issue date
Mar 8, 2011
Lattice Semiconductor Corporation
Chan-Chi Jason Cheng
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Redundant configuration memory systems and methods
Patent number
7,746,107
Issue date
Jun 29, 2010
Lattice Semiconductor Corporation
Satwant Singh
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Multiplexer initialization systems and methods
Patent number
7,663,401
Issue date
Feb 16, 2010
Lattice Semiconductor Corporation
Chi Minh Nguyen
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Redundant configuration memory systems and methods
Patent number
7,598,765
Issue date
Oct 6, 2009
Lattice Semiconductor Corporation
Satwant Singh
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
High fan-out signal routing systems and methods
Patent number
7,576,563
Issue date
Aug 18, 2009
Lattice Semiconductor Corporation
Qin Wei
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Programmable logic device with enhanced logic block architecture
Patent number
7,573,291
Issue date
Aug 11, 2009
Lattice Semiconductor Corporation
Om Agrawal
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Programmable logic device with enhanced logic block architecture
Patent number
7,295,035
Issue date
Nov 13, 2007
Lattice Semiconductor Corporation
Om Agrawal
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
FIFO memory with programmable data port widths
Patent number
6,986,004
Issue date
Jan 10, 2006
Lattice Semiconductor Corporation
Chan-Chi Jason Cheng
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
CPLD with multi-function blocks and distributed memory
Patent number
6,879,182
Issue date
Apr 12, 2005
Lattice Semiconductor Corporation
Om P. Agrawal
G11 - INFORMATION STORAGE
Information
Patent Grant
Cascaded logic block architecture for complex programmable logic de...
Patent number
6,861,871
Issue date
Mar 1, 2005
Lattice Semiconductor Corporation
Om P. Agrawal
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Non-volatile and reconfigurable programmable logic devices
Patent number
6,828,823
Issue date
Dec 7, 2004
Lattice Semiconductor Corporation
Cyrus Tsui
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Structure and method for multiplexing pins for in-system programming
Patent number
5,336,951
Issue date
Aug 9, 1994
Lattice Semiconductor Corporation
Gregg R. Josephson
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Structure and method for multiplexing pins for in-system programming
Patent number
5,237,218
Issue date
Aug 17, 1993
Lattice Semiconductor Corporation
Gregg R. Josephson
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Sense amplifier with depletion transistor feedback
Patent number
5,162,679
Issue date
Nov 10, 1992
Lattice Semiconductor Corporation
Ju Shen
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Integrated programmable logic device with control circuit to power...
Patent number
5,138,198
Issue date
Aug 11, 1992
Lattice Semiconductor Corporation
Ju Shen
H03 - BASIC ELECTRONIC CIRCUITRY
Patents Applications
last 30 patents
Information
Patent Application
REDUNDANT CONFIGURATION MEMORY SYSTEMS AND METHODS
Publication number
20080204073
Publication date
Aug 28, 2008
Satwant Singh
H03 - BASIC ELECTRONIC CIRCUITRY