Chan-Sui Pang

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Word line compensation in non-volatile memory erase operations
- Patent number 7,606,074
- Issue date Oct 20, 2009
- SanDisk Corporation
- Jun Wan
- G11 - INFORMATION STORAGE
Information Patent Grant
Word line compensation in non-volatile memory erase operations
- Patent number 7,450,433
- Issue date Nov 11, 2008
- SanDisk Corporation
- Jun Wan
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash memory programming using gate induced junction leakage current
- Patent number 7,057,931
- Issue date Jun 6, 2006
- SanDisk Corporation
- Jeffrey W. Lutze
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual-bit double-polysilicon source-side injection flash EEPROM cell
- Patent number 6,798,012
- Issue date Sep 28, 2004
- Yueh Yale Ma
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of operation of a dual-bit double-polysilicon source-side in...
- Patent number 6,714,454
- Issue date Mar 30, 2004
- Yueh Yale Ma
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for operating nonvolatile memory cells
- Patent number 6,493,262
- Issue date Dec 10, 2002
- Winbond Electronics Corporation
- Keith R. Wald
- G11 - INFORMATION STORAGE
Information Patent Grant
Programming current limiter for source-side injection EEPROM cells
- Patent number 5,986,941
- Issue date Nov 16, 1999
- Bright Microelectronics, Inc.
- Chan-Sui Pang
- G11 - INFORMATION STORAGE
Information Patent Grant
Switch driver circuit for providing small sector sizes for negative...
- Patent number 5,663,907
- Issue date Sep 2, 1997
- Bright Microelectronics, Inc.
- Jack E. Frayer
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory array architecture for flash memory
- Patent number 5,185,718
- Issue date Feb 9, 1993
- Catalyst Semiconductor Corporation
- Darrell D. Rinerson
- G11 - INFORMATION STORAGE
Information Patent Grant
High density EEPROM cell and process for making the cell
- Patent number 5,033,023
- Issue date Jul 16, 1991
- Catalyst Semiconductor, Inc.
- Steve K. Hsia
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile memory cell for eeprom including a floating gate to dra...
- Patent number 4,894,802
- Issue date Jan 16, 1990
- Catalyst Semiconductor, Inc.
- Steve K. Hsia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High-reliablity single-poly eeprom cell
- Patent number 4,807,003
- Issue date Feb 21, 1989
- National Semiconductor Corp.
- Farrokh Mohammadi
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Word Line Compensation In Non-Volatile Memory Erase Operations
- Publication number 20090021983
- Publication date Jan 22, 2009
- SANDISK CORPORATION
- Jun Wan
- G11 - INFORMATION STORAGE
Information Patent Application
Word line compensation in non-volatile memory erase operations
- Publication number 20060140012
- Publication date Jun 29, 2006
- Jun Wan
- G11 - INFORMATION STORAGE
Information Patent Application
Flash memory programming using gate induced junction leakage current
- Publication number 20050099849
- Publication date May 12, 2005
- Jeffrey W. Lutze
- G11 - INFORMATION STORAGE
Information Patent Application
Method for erasing a nonvolatile memory cell formed in a body regio...
- Publication number 20030071301
- Publication date Apr 17, 2003
- Winbond Electronics Corporation
- Keith R. Wald
- G11 - INFORMATION STORAGE
Information Patent Application
Method of operation of a dual-bit double-polysilicon source-side in...
- Publication number 20030057474
- Publication date Mar 27, 2003
- Yueh Yale Ma
- H01 - BASIC ELECTRIC ELEMENTS

Chan-Sui Pang

Person

Patents Grantslast 30 patents

Word line compensation in non-volatile memory erase operations

Word line compensation in non-volatile memory erase operations

Flash memory programming using gate induced junction leakage current

Dual-bit double-polysilicon source-side injection flash EEPROM cell

Method of operation of a dual-bit double-polysilicon source-side in...

Method for operating nonvolatile memory cells

Programming current limiter for source-side injection EEPROM cells

Switch driver circuit for providing small sector sizes for negative...

Memory array architecture for flash memory

High density EEPROM cell and process for making the cell

Nonvolatile memory cell for eeprom including a floating gate to dra...

High-reliablity single-poly eeprom cell

Patents Applicationslast 30 patents

Word Line Compensation In Non-Volatile Memory Erase Operations

Word line compensation in non-volatile memory erase operations

Flash memory programming using gate induced junction leakage current

Method for erasing a nonvolatile memory cell formed in a body regio...

Method of operation of a dual-bit double-polysilicon source-side in...