Chanaka D. Munasinghe

Person

Hillsboro, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Non-planar semiconductor device having doped sub-fin region and met...
- Patent number 12,191,308
- Issue date Jan 7, 2025
- Tahoe Research, LTD.
- Tahir Ghani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-planar semiconductor device having doped sub-fin region and met...
- Patent number 11,631,673
- Issue date Apr 18, 2023
- Tahoe Research, LTD.
- Tahir Ghani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-planar semiconductor device having doped sub-fin region and met...
- Patent number 10,964,697
- Issue date Mar 30, 2021
- Intel Corporation
- Tahir Ghani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Isolation well doping with solid-state diffusion sources for finFET...
- Patent number 10,854,607
- Issue date Dec 1, 2020
- Intel Corporation
- Chia-Hong Jan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Doping with solid-state diffusion sources for finFET architectures
- Patent number 10,643,999
- Issue date May 5, 2020
- Intel Corporation
- Chia-Hong Jan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-planar semiconductor device having doped sub-fin region and met...
- Patent number 10,622,359
- Issue date Apr 14, 2020
- Intel Corporation
- Tahir Ghani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-planar semiconductor device having doped sub-fin region and met...
- Patent number 10,396,079
- Issue date Aug 27, 2019
- Intel Corporation
- Tahir Ghani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Doping with solid-state diffusion sources for finFET architectures
- Patent number 10,340,273
- Issue date Jul 2, 2019
- Intel Corporation
- Chia-Hong Jan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Isolation well doping with solid-state diffusion sources for FinFET...
- Patent number 10,090,304
- Issue date Oct 2, 2018
- Intel Corporation
- Chia-Hong Jan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-planar semiconductor device having doped sub-fin region and met...
- Patent number 10,056,380
- Issue date Aug 21, 2018
- Intel Corporation
- Tahir Ghani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Double patterning lithography techniques
- Patent number 9,142,421
- Issue date Sep 22, 2015
- Intel Corporation
- Charles H. Wallace
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT STRUCTURES WITH TRENCH CONTACT SPACER STRUCTURE
- Publication number 20250210510
- Publication date Jun 26, 2025
- Intel Corporation
- Rohan BAMBERY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURE WITH DEEP VIA BAR ISOLATION
- Publication number 20240429125
- Publication date Dec 26, 2024
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED VIA PATTERNING FOR BACKSIDE INTERCONNECTS
- Publication number 20240404917
- Publication date Dec 5, 2024
- Intel Corporation
- Sikandar Abbas
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RECESSED TRANSISTOR TERMINAL VIA JUMPERS
- Publication number 20230320057
- Publication date Oct 5, 2023
- Intel Corporation
- Clifford Ong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES WITH PRE-EPITAXIAL DEEP VIA STRUCTURE
- Publication number 20230317595
- Publication date Oct 5, 2023
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONTACT OVER ACTIVE GATE STRUCTURES WITH UNIFORM AND CONFORMAL GATE...
- Publication number 20230290843
- Publication date Sep 14, 2023
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TOPSIDE PLUGS FOR EPITAXIAL CONTACT FORMATION
- Publication number 20230282717
- Publication date Sep 7, 2023
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED INTERCONNECT FEATURES FOR TRANSISTOR CONTACTS
- Publication number 20230282575
- Publication date Sep 7, 2023
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NON-PLANAR SEMICONDUCTOR DEVICE HAVING DOPED SUB-FIN REGION AND MET...
- Publication number 20230223406
- Publication date Jul 13, 2023
- Tahoe Research, Ltd.
- Tahir GHANI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RECESSED AND SELF-ALIGNED BURIED POWER RAIL
- Publication number 20230207466
- Publication date Jun 29, 2023
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES WITH TRENCH CONTACT FLYOVER STRUCTURE
- Publication number 20230187441
- Publication date Jun 15, 2023
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SILICON RICH CAPPING LAYER PRE-AMORPHIZED WITH GERMANIUM AND BORON...
- Publication number 20230101725
- Publication date Mar 30, 2023
- Intel Corporation
- Debaleena NANDI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING CUT METAL GATES WITH DIELECTRI...
- Publication number 20220399373
- Publication date Dec 15, 2022
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NON-PLANAR SEMICONDUCTOR DEVICE HAVING DOPED SUB-FIN REGION AND MET...
- Publication number 20210175233
- Publication date Jun 10, 2021
- Intel Corporation
- TAHIR GHANI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ISOLATION WELL DOPING WITH SOLID-STATE DIFFUSION SOURCES FOR FINFET...
- Publication number 20200251471
- Publication date Aug 6, 2020
- Intel Corporation
- Chia-Hong Jan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NON-PLANAR SEMICONDUCTOR DEVICE HAVING DOPED SUB-FIN REGION AND MET...
- Publication number 20200212039
- Publication date Jul 2, 2020
- Intel Corporation
- TAHIR GHANI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NON-PLANAR SEMICONDUCTOR DEVICE HAVING DOPED SUB-FIN REGION AND MET...
- Publication number 20190341383
- Publication date Nov 7, 2019
- Intel Corporation
- TAHIR GHANI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DOPING WITH SOLID-STATE DIFFUSION SOURCES FOR FINFET ARCHITECTURES
- Publication number 20190287973
- Publication date Sep 19, 2019
- Intel Corporation
- Chia-Hong Jan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NON-PLANAR SEMICONDUCTOR DEVICE HAVING DOPED SUB-FIN REGION AND MET...
- Publication number 20190006362
- Publication date Jan 3, 2019
- Intel Corporation
- TAHIR GHANI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DOPING WITH SOLID-STATE DIFFUSION SOURCES FOR FINFET ARCHITECTURES
- Publication number 20170125419
- Publication date May 4, 2017
- Intel Corporation
- Chia-Hong Jan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ISOLATION WELL DOPING WITH SOLID-STATE DIFFUSION SOURCES FOR FINFET...
- Publication number 20160211262
- Publication date Jul 21, 2016
- CHIA-HONG JAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NON-PLANAR SEMICONDUCTOR DEVICE HAVING DOPED SUB-FIN REGION AND MET...
- Publication number 20160056156
- Publication date Feb 25, 2016
- Intel Corporation
- TAHIR GHANI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DOUBLE PATTERNING LITHOGRAPHY TECHNIQUES
- Publication number 20140017899
- Publication date Jan 16, 2014
- Charles H. Wallace
- H01 - BASIC ELECTRIC ELEMENTS

Chanaka D. Munasinghe

Person

Patents Grantslast 30 patents

Non-planar semiconductor device having doped sub-fin region and met...

Non-planar semiconductor device having doped sub-fin region and met...

Non-planar semiconductor device having doped sub-fin region and met...

Isolation well doping with solid-state diffusion sources for finFET...

Doping with solid-state diffusion sources for finFET architectures

Non-planar semiconductor device having doped sub-fin region and met...

Non-planar semiconductor device having doped sub-fin region and met...

Doping with solid-state diffusion sources for finFET architectures

Isolation well doping with solid-state diffusion sources for FinFET...

Non-planar semiconductor device having doped sub-fin region and met...

Double patterning lithography techniques

Patents Applicationslast 30 patents

INTEGRATED CIRCUIT STRUCTURES WITH TRENCH CONTACT SPACER STRUCTURE

INTEGRATED CIRCUIT STRUCTURE WITH DEEP VIA BAR ISOLATION

SELF-ALIGNED VIA PATTERNING FOR BACKSIDE INTERCONNECTS

RECESSED TRANSISTOR TERMINAL VIA JUMPERS

INTEGRATED CIRCUIT STRUCTURES WITH PRE-EPITAXIAL DEEP VIA STRUCTURE

CONTACT OVER ACTIVE GATE STRUCTURES WITH UNIFORM AND CONFORMAL GATE...

TOPSIDE PLUGS FOR EPITAXIAL CONTACT FORMATION

SELF-ALIGNED INTERCONNECT FEATURES FOR TRANSISTOR CONTACTS

NON-PLANAR SEMICONDUCTOR DEVICE HAVING DOPED SUB-FIN REGION AND MET...

RECESSED AND SELF-ALIGNED BURIED POWER RAIL

INTEGRATED CIRCUIT STRUCTURES WITH TRENCH CONTACT FLYOVER STRUCTURE

SILICON RICH CAPPING LAYER PRE-AMORPHIZED WITH GERMANIUM AND BORON...

INTEGRATED CIRCUIT STRUCTURES HAVING CUT METAL GATES WITH DIELECTRI...

NON-PLANAR SEMICONDUCTOR DEVICE HAVING DOPED SUB-FIN REGION AND MET...

ISOLATION WELL DOPING WITH SOLID-STATE DIFFUSION SOURCES FOR FINFET...

NON-PLANAR SEMICONDUCTOR DEVICE HAVING DOPED SUB-FIN REGION AND MET...

NON-PLANAR SEMICONDUCTOR DEVICE HAVING DOPED SUB-FIN REGION AND MET...

DOPING WITH SOLID-STATE DIFFUSION SOURCES FOR FINFET ARCHITECTURES

NON-PLANAR SEMICONDUCTOR DEVICE HAVING DOPED SUB-FIN REGION AND MET...

DOPING WITH SOLID-STATE DIFFUSION SOURCES FOR FINFET ARCHITECTURES

ISOLATION WELL DOPING WITH SOLID-STATE DIFFUSION SOURCES FOR FINFET...

NON-PLANAR SEMICONDUCTOR DEVICE HAVING DOPED SUB-FIN REGION AND MET...

DOUBLE PATTERNING LITHOGRAPHY TECHNIQUES