Chandrasekhar S Thyamagondlu

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Descriptor fetching for a multi-queue direct memory access system
- Patent number 12,259,833
- Issue date Mar 25, 2025
- Xilinx, Inc.
- Chandrasekhar S. Thyamagondlu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-host direct memory access system for integrated circuits
- Patent number 11,726,936
- Issue date Aug 15, 2023
- Xilinx, Inc.
- Chandrasekhar S. Thyamagondlu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Virtual hot plug system and method for PCIe devices
- Patent number 11,256,648
- Issue date Feb 22, 2022
- Xilinx, Inc.
- Chuan Cheng Pan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-host direct memory access system for integrated circuits
- Patent number 11,232,053
- Issue date Jan 25, 2022
- Xilinx, Inc.
- Chandrasekhar S. Thyamagondlu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bootstrapping a programmable integrated circuit based network inter...
- Patent number 11,055,106
- Issue date Jul 6, 2021
- Xilinx, Inc.
- Ellery Cochell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamically reconfigurable networking using a programmable integrat...
- Patent number 10,990,547
- Issue date Apr 27, 2021
- Xilinx, Inc.
- Chandrasekhar S. Thyamagondlu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Customizable multi queue DMA interface
- Patent number 10,983,920
- Issue date Apr 20, 2021
- Xilinx, Inc.
- Chandrasekhar S Thyamagondlu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Streaming platform flow and architecture for an integrated circuit
- Patent number 10,924,430
- Issue date Feb 16, 2021
- Xilinx, Inc.
- Chandrasekhar S. Thyamagondlu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Streaming platform architecture for inter-kernel circuit communicat...
- Patent number 10,725,942
- Issue date Jul 28, 2020
- Xilinx, Inc.
- Chandrasekhar S. Thyamagondlu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interrupt moderation and aggregation circuitry
- Patent number 10,657,084
- Issue date May 19, 2020
- Xilinx, Inc.
- Chandrasekhar S. Thyamagondlu
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MULTI-HOST AND MULTI-CLIENT DIRECT MEMORY ACCESS SYSTEM HAVING A RE...
- Publication number 20250004961
- Publication date Jan 2, 2025
- Xilinx, Inc.
- Chandrasekhar S. Thyamagondlu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESCRIPTOR FETCHING FOR A MULTI-QUEUE DIRECT MEMORY ACCESS SYSTEM
- Publication number 20240330215
- Publication date Oct 3, 2024
- Xilinx, Inc.
- Chandrasekhar S. Thyamagondlu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIRECT MEMORY ACCESS SYSTEM WITH READ REASSEMBLY CIRCUIT
- Publication number 20240330216
- Publication date Oct 3, 2024
- Xilinx, Inc.
- Chandrasekhar S. Thyamagondlu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VARIABLE BUFFER SIZE DESCRIPTOR FETCHING FOR A MULTI-QUEUE DIRECT M...
- Publication number 20240330213
- Publication date Oct 3, 2024
- Xilinx, Inc.
- Chandrasekhar S. Thyamagondlu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESCRIPTOR CACHE EVICTION FOR MULTI-QUEUE DIRECT MEMORY ACCESS
- Publication number 20240330191
- Publication date Oct 3, 2024
- Xilinx, Inc.
- Chandrasekhar S. Thyamagondlu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FIREWALLING COMMUNICATION PORTS IN A MULTI-PORT SYSTEM
- Publication number 20240314107
- Publication date Sep 19, 2024
- Xilinx, Inc.
- Chandrasekhar S. Thyamagondlu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA BUS WIDTH CONFIGURABLE INTERCONNECTION CIRCUITRY
- Publication number 20240273047
- Publication date Aug 15, 2024
- Xilinx, Inc.
- Surender Reddy KISANAGAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-HOST DIRECT MEMORY ACCESS SYSTEM FOR INTEGRATED CIRCUITS
- Publication number 20220092010
- Publication date Mar 24, 2022
- Xilinx, Inc.
- Chandrasekhar S. Thyamagondlu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMICALLY RECONFIGURABLE NETWORKING USING A PROGRAMMABLE INTEGRAT...
- Publication number 20210042252
- Publication date Feb 11, 2021
- Xilinx, Inc.
- Chandrasekhar S. Thyamagondlu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STREAMING PLATFORM FLOW AND ARCHITECTURE
- Publication number 20200153756
- Publication date May 14, 2020
- Xilinx, Inc.
- Chandrasekhar S. Thyamagondlu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STREAMING PLATFORM ARCHITECTURE FOR INTER-KERNEL CIRCUIT COMMUNICAT...
- Publication number 20200151120
- Publication date May 14, 2020
- Xilinx, Inc.
- Chandrasekhar S. Thyamagondlu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CUSTOMIZABLE MULTI QUEUE DMA INTERFACE
- Publication number 20190243781
- Publication date Aug 8, 2019
- Xilinx, Inc.
- Chandrasekhar S Thyamagondlu
- G06 - COMPUTING CALCULATING COUNTING

Chandrasekhar S Thyamagondlu

Person

Patents Grantslast 30 patents

Descriptor fetching for a multi-queue direct memory access system

Multi-host direct memory access system for integrated circuits

Virtual hot plug system and method for PCIe devices

Multi-host direct memory access system for integrated circuits

Bootstrapping a programmable integrated circuit based network inter...

Dynamically reconfigurable networking using a programmable integrat...

Customizable multi queue DMA interface

Streaming platform flow and architecture for an integrated circuit

Streaming platform architecture for inter-kernel circuit communicat...

Interrupt moderation and aggregation circuitry

Patents Applicationslast 30 patents

MULTI-HOST AND MULTI-CLIENT DIRECT MEMORY ACCESS SYSTEM HAVING A RE...

DESCRIPTOR FETCHING FOR A MULTI-QUEUE DIRECT MEMORY ACCESS SYSTEM

DIRECT MEMORY ACCESS SYSTEM WITH READ REASSEMBLY CIRCUIT

VARIABLE BUFFER SIZE DESCRIPTOR FETCHING FOR A MULTI-QUEUE DIRECT M...

DESCRIPTOR CACHE EVICTION FOR MULTI-QUEUE DIRECT MEMORY ACCESS

FIREWALLING COMMUNICATION PORTS IN A MULTI-PORT SYSTEM

DATA BUS WIDTH CONFIGURABLE INTERCONNECTION CIRCUITRY

MULTI-HOST DIRECT MEMORY ACCESS SYSTEM FOR INTEGRATED CIRCUITS

DYNAMICALLY RECONFIGURABLE NETWORKING USING A PROGRAMMABLE INTEGRAT...

STREAMING PLATFORM FLOW AND ARCHITECTURE

STREAMING PLATFORM ARCHITECTURE FOR INTER-KERNEL CIRCUIT COMMUNICAT...

CUSTOMIZABLE MULTI QUEUE DMA INTERFACE