Chang Wan Ha

Person

San Ramon, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Asymmetric junctions of high voltage transistor in NAND flash memory
- Patent number 11,653,496
- Issue date May 16, 2023
- Intel Corporation
- Chang Wan Ha
- G11 - INFORMATION STORAGE
Information Patent Grant
Reducing power consumption in nonvolatile memory due to standby lea...
- Patent number 11,500,446
- Issue date Nov 15, 2022
- Intel Corporation
- Richard Fastow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Defective bit line management in connection with a memory access
- Patent number 11,429,469
- Issue date Aug 30, 2022
- Intel Corporation
- Ali Khakifirooz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Devices including stair step structures, and related apparatuses an...
- Patent number 11,393,716
- Issue date Jul 19, 2022
- Micron Technology, Inc.
- Chang Wan Ha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Defective bit line management in connection with a memory access
- Patent number 10,942,799
- Issue date Mar 9, 2021
- Intel Corporation
- Ali Khakifirooz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Program verification time reduction in non-volatile memory devices
- Patent number 10,832,766
- Issue date Nov 10, 2020
- Intel Corporation
- Ali Khakifirooz
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory devices and related methods
- Patent number 10,748,811
- Issue date Aug 18, 2020
- Micron Technology, Inc.
- Chang Wan Ha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of operating a memory device
- Patent number 10,468,116
- Issue date Nov 5, 2019
- Micron Technology, Inc.
- Chang Wan Ha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power management
- Patent number 10,365,703
- Issue date Jul 30, 2019
- Micron Technology, Inc.
- Chang Wan Ha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Testing impedance adjustment
- Patent number 10,348,527
- Issue date Jul 9, 2019
- Micron Technology, Inc.
- Qiang Tang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stair step formation using at least two masks
- Patent number 10,269,626
- Issue date Apr 23, 2019
- Micron Technology, Inc.
- Chang Wan Ha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Testing impedance adjustment
- Patent number 9,912,498
- Issue date Mar 6, 2018
- Micron Technology, Inc.
- Qiang Tang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Power management
- Patent number 9,880,609
- Issue date Jan 30, 2018
- Micron Technology, Inc.
- Chang Wan Ha
- G11 - INFORMATION STORAGE
Information Patent Grant
Stair step formation using at least two masks
- Patent number 9,870,941
- Issue date Jan 16, 2018
- Micron Technology, Inc.
- Chang Wan Ha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatuses and methods for operating a memory device
- Patent number 9,831,002
- Issue date Nov 28, 2017
- Micron Technology, Inc.
- Chang Wan Ha
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic data caches, decoders and decoding methods
- Patent number 9,672,156
- Issue date Jun 6, 2017
- Micron Technology, Inc.
- Chang Wan Ha
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor devices including stair step structures, and related...
- Patent number 9,659,950
- Issue date May 23, 2017
- Micron Technology, Inc.
- Aaron Yip
- G11 - INFORMATION STORAGE
Information Patent Grant
Stair step formation using at least two masks
- Patent number 9,508,591
- Issue date Nov 29, 2016
- Micron Technology, Inc.
- Chang Wan Ha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Column address decoding
- Patent number 9,431,110
- Issue date Aug 30, 2016
- Intel Corporation
- Chang W. Ha
- G11 - INFORMATION STORAGE
Information Patent Grant
Power management
- Patent number 9,417,685
- Issue date Aug 16, 2016
- Micron Technology, Inc.
- Chang Wan Ha
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic data caches, decoders and decoding methods
- Patent number 9,299,442
- Issue date Mar 29, 2016
- Micron Technologies, Inc.
- Chang Wan Ha
- G11 - INFORMATION STORAGE
Information Patent Grant
Sub-block disabling in 3D memory
- Patent number 9,263,111
- Issue date Feb 16, 2016
- Micron Technology, Inc.
- Chang Wan Ha
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor devices including stair step structures, and related...
- Patent number 9,165,937
- Issue date Oct 20, 2015
- Micron Technology, Inc.
- Aaron Yip
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatuses and methods for operating a memory device
- Patent number 9,158,607
- Issue date Oct 13, 2015
- Micron Technology, Inc.
- Chang Wan Ha
- G11 - INFORMATION STORAGE
Information Patent Grant
Stair step formation using at least two masks
- Patent number 9,082,772
- Issue date Jul 14, 2015
- Micron Technology, Inc.
- Chang Wan Ha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Using a reference bit line in a memory
- Patent number 9,042,187
- Issue date May 26, 2015
- Intel Corporation
- Chang Wan Ha
- G11 - INFORMATION STORAGE
Information Patent Grant
Sub-block disabling in 3D memory
- Patent number 9,007,860
- Issue date Apr 14, 2015
- Micron Technology, Inc.
- Chang Wan Ha
- G11 - INFORMATION STORAGE
Information Patent Grant
Sub-block decoding in 3D memory
- Patent number 9,001,584
- Issue date Apr 7, 2015
- Micron Technology, Inc.
- Chang Wan Ha
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic data caches, decoders and decoding methods
- Patent number 8,711,633
- Issue date Apr 29, 2014
- Micron Technology, Inc.
- Chang Wan Ha
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for reading a multilevel cell in a non-volatile memory device
- Patent number 8,656,092
- Issue date Feb 18, 2014
- Micron Technology, Inc.
- Chang Wan Ha
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
SYNCHRONOUS INDEPENDENT PLANE READ OPERATION
- Publication number 20230317144
- Publication date Oct 5, 2023
- Intel NDTM US LLC
- Chang Wan Ha
- G11 - INFORMATION STORAGE
Information Patent Application
INTERFACE FOR DIFFERENT INTERNAL AND EXTERNAL MEMORY IO PATHS
- Publication number 20230305708
- Publication date Sep 28, 2023
- Intel NDTM US LLC
- Chang Wan Ha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS TO SELECT A PLANE IN A NAND FLASH DIE TO STORE...
- Publication number 20230266910
- Publication date Aug 24, 2023
- Intel NDTM US LLC
- Chang Wan HA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS TO REDUCE POWER CONSUMPTION OF PAGE BUFFER CIR...
- Publication number 20230230639
- Publication date Jul 20, 2023
- Intel NDTM US LLC
- Mattia CICHOCKI
- G11 - INFORMATION STORAGE
Information Patent Application
PARALLEL STAIRCASE 3D NAND
- Publication number 20230200063
- Publication date Jun 22, 2023
- Intel Corporation
- Deepak Thimmegowda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GROUPED GLOBAL WORDLINE DRIVER WITH SHARED BIAS SCHEME
- Publication number 20230082368
- Publication date Mar 16, 2023
- Intel Corporation
- Chang Wan Ha
- G11 - INFORMATION STORAGE
Information Patent Application
SPLIT BLOCK ARRAY FOR 3D NAND MEMORY
- Publication number 20220399057
- Publication date Dec 15, 2022
- Intel Corporation
- Chang Wan Ha
- G11 - INFORMATION STORAGE
Information Patent Application
ASYMMETRIC JUNCTIONS OF HIGH VOLTAGE TRANSISTOR IN NAND FLASH MEMORY
- Publication number 20220102365
- Publication date Mar 31, 2022
- Intel Corporation
- Chang Wan HA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEFECTIVE BIT LINE MANAGEMENT IN CONNECTION WITH A MEMORY ACCESS
- Publication number 20210193200
- Publication date Jun 24, 2021
- Intel Corporation
- Ali KHAKIFIROOZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCING POWER CONSUMPTION IN NONVOLATILE MEMORY DUE TO STANDBY LEA...
- Publication number 20210096634
- Publication date Apr 1, 2021
- Intel Corporation
- Richard FASTOW
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEFECTIVE BIT LINE MANAGEMENT IN CONNECTION WITH A MEMORY ACCESS
- Publication number 20210074338
- Publication date Mar 11, 2021
- Intel Corporation
- Ali KHAKIFIROOZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICES INCLUDING STAIR STEP STRUCTURES, AND RELATED APPARATUSES AN...
- Publication number 20200365452
- Publication date Nov 19, 2020
- Micron Technology, Inc.
- Chang Wan Ha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY DEVICES AND RELATED METHODS
- Publication number 20190237362
- Publication date Aug 1, 2019
- Micron Technology, Inc.
- Chang Wan Ha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROGRAM VERIFICATION TIME REDUCTION IN NON-VOLATILE MEMORY DEVICES
- Publication number 20190043563
- Publication date Feb 7, 2019
- Ali Khakifirooz
- G11 - INFORMATION STORAGE
Information Patent Application
TESTING IMPEDANCE ADJUSTMENT
- Publication number 20180191528
- Publication date Jul 5, 2018
- Micron Technology, Inc.
- Qiang Tang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER MANAGEMENT
- Publication number 20180136707
- Publication date May 17, 2018
- Micron Technology, Inc.
- Chang Wan HA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STAIR STEP FORMATION USING AT LEAST TWO MASKS
- Publication number 20180130700
- Publication date May 10, 2018
- Micron Technology, Inc.
- Chang Wan Ha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF OPERATING A MEMORY DEVICE
- Publication number 20170365358
- Publication date Dec 21, 2017
- Micron Technology, Inc.
- Chang Wan Ha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STAIR STEP FORMATION USING AT LEAST TWO MASKS
- Publication number 20170076977
- Publication date Mar 16, 2017
- Micron Technology, Inc.
- Chang Wan Ha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POWER MANAGEMENT
- Publication number 20160342187
- Publication date Nov 24, 2016
- Micron Technology, Inc.
- Chang Wan Ha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TESTING IMPEDANCE ADJUSTMENT
- Publication number 20160258997
- Publication date Sep 8, 2016
- Micron Technology, Inc.
- Qiang Tang
- G01 - MEASURING TESTING
Information Patent Application
DYNAMIC DATA CACHES, DECODERS AND DECODING METHODS
- Publication number 20160210236
- Publication date Jul 21, 2016
- Micron Technology, Inc.
- Chang Wan Ha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR OPERATING A MEMORY DEVICE
- Publication number 20160035436
- Publication date Feb 4, 2016
- Micron Technology, Inc.
- Chang Wan Ha
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICES INCLUDING STAIR STEP STRUCTURES, AND RELATED...
- Publication number 20160027793
- Publication date Jan 28, 2016
- Micron Technology, Inc.
- Aaron Yip
- G11 - INFORMATION STORAGE
Information Patent Application
STAIR STEP FORMATION USING AT LEAST TWO MASKS
- Publication number 20150318203
- Publication date Nov 5, 2015
- Micron Technology, Inc.
- Chang Wan Ha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUB-BLOCK DISABLING IN 3D MEMORY
- Publication number 20150213863
- Publication date Jul 30, 2015
- Micron Technology, Inc.
- Chang Wan Ha
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICES INCLUDING STAIR STEP STRUCTURES, AND RELATED...
- Publication number 20150001613
- Publication date Jan 1, 2015
- Micron Technology, Inc.
- Aaron Yip
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUB-BLOCK DECODING IN 3D MEMORY
- Publication number 20140241060
- Publication date Aug 28, 2014
- Micron Technology, Inc.
- Chang Wan Ha
- G11 - INFORMATION STORAGE
Information Patent Application
SUB-BLOCK DISABLING IN 3D MEMORY
- Publication number 20140241092
- Publication date Aug 28, 2014
- Micron Technology, Inc.
- Chang Wan Ha
- G11 - INFORMATION STORAGE
Information Patent Application
DYNAMIC DATA CACHES, DECODERS AND DECODING METHODS
- Publication number 20140233318
- Publication date Aug 21, 2014
- Micron Technology Inc.
- Chang Wan Ha
- G06 - COMPUTING CALCULATING COUNTING

Chang Wan Ha

Person

Patents Grantslast 30 patents

Asymmetric junctions of high voltage transistor in NAND flash memory

Reducing power consumption in nonvolatile memory due to standby lea...

Defective bit line management in connection with a memory access

Devices including stair step structures, and related apparatuses an...

Defective bit line management in connection with a memory access

Program verification time reduction in non-volatile memory devices

Memory devices and related methods

Methods of operating a memory device

Power management

Testing impedance adjustment

Stair step formation using at least two masks

Testing impedance adjustment

Power management

Stair step formation using at least two masks

Apparatuses and methods for operating a memory device

Dynamic data caches, decoders and decoding methods

Semiconductor devices including stair step structures, and related...

Stair step formation using at least two masks

Column address decoding

Power management

Dynamic data caches, decoders and decoding methods

Sub-block disabling in 3D memory

Semiconductor devices including stair step structures, and related...

Apparatuses and methods for operating a memory device

Stair step formation using at least two masks

Using a reference bit line in a memory

Sub-block disabling in 3D memory

Sub-block decoding in 3D memory

Dynamic data caches, decoders and decoding methods

Method for reading a multilevel cell in a non-volatile memory device

Patents Applicationslast 30 patents

SYNCHRONOUS INDEPENDENT PLANE READ OPERATION

INTERFACE FOR DIFFERENT INTERNAL AND EXTERNAL MEMORY IO PATHS

METHOD AND APPARATUS TO SELECT A PLANE IN A NAND FLASH DIE TO STORE...

METHOD AND APPARATUS TO REDUCE POWER CONSUMPTION OF PAGE BUFFER CIR...

PARALLEL STAIRCASE 3D NAND

GROUPED GLOBAL WORDLINE DRIVER WITH SHARED BIAS SCHEME

SPLIT BLOCK ARRAY FOR 3D NAND MEMORY

ASYMMETRIC JUNCTIONS OF HIGH VOLTAGE TRANSISTOR IN NAND FLASH MEMORY

DEFECTIVE BIT LINE MANAGEMENT IN CONNECTION WITH A MEMORY ACCESS

REDUCING POWER CONSUMPTION IN NONVOLATILE MEMORY DUE TO STANDBY LEA...

DEFECTIVE BIT LINE MANAGEMENT IN CONNECTION WITH A MEMORY ACCESS

DEVICES INCLUDING STAIR STEP STRUCTURES, AND RELATED APPARATUSES AN...

MEMORY DEVICES AND RELATED METHODS

PROGRAM VERIFICATION TIME REDUCTION IN NON-VOLATILE MEMORY DEVICES

TESTING IMPEDANCE ADJUSTMENT

POWER MANAGEMENT

STAIR STEP FORMATION USING AT LEAST TWO MASKS

METHODS OF OPERATING A MEMORY DEVICE

STAIR STEP FORMATION USING AT LEAST TWO MASKS

POWER MANAGEMENT

TESTING IMPEDANCE ADJUSTMENT

DYNAMIC DATA CACHES, DECODERS AND DECODING METHODS

APPARATUSES AND METHODS FOR OPERATING A MEMORY DEVICE

SEMICONDUCTOR DEVICES INCLUDING STAIR STEP STRUCTURES, AND RELATED...

STAIR STEP FORMATION USING AT LEAST TWO MASKS

SUB-BLOCK DISABLING IN 3D MEMORY

SEMICONDUCTOR DEVICES INCLUDING STAIR STEP STRUCTURES, AND RELATED...

SUB-BLOCK DECODING IN 3D MEMORY

SUB-BLOCK DISABLING IN 3D MEMORY

DYNAMIC DATA CACHES, DECODERS AND DECODING METHODS