Chao-Wen TZENG

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Taichung City, TW

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Patents Grantslast 30 patents

Information Patent Grant
Clock edge detection device and method
- Patent number 9,160,322
- Issue date Oct 13, 2015
- Realtek Semiconductor Corporation
- Yu-Cheng Lo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
PLL status detection circuit and method thereof
- Patent number 9,157,957
- Issue date Oct 13, 2015
- Realtek Semiconductor Corporation
- Chao-Wen Tzeng
- G01 - MEASURING TESTING
Information Patent Grant
Delay difference detection and adjustment device and method
- Patent number 8,907,709
- Issue date Dec 9, 2014
- Realtek Semiconductor Corporation
- Yu-Cheng Lo
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Clock edge detection device and method
- Publication number 20150022242
- Publication date Jan 22, 2015
- REALTEK SEMICONDUCTOR CORPORATION
- Yu-Cheng LO
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Multi-Phase Clock Generation System and Clock Calibration Method Th...
- Publication number 20130088268
- Publication date Apr 11, 2013
- TINNOTEK INC.
- Ruo-Ting Ding
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PHASE-LOCKED LOOP DEVICE AND CLOCK CALIBRATION METHOD THEREOF
- Publication number 20120133444
- Publication date May 31, 2012
- TINNOTEK INC.
- CHAO-WEN TZENG
- H03 - BASIC ELECTRONIC CIRCUITRY