Charan Gurumurthy

Person

Gilbert, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method of forming a substrate core structure using microvia laser d...
- Patent number 10,306,760
- Issue date May 28, 2019
- Intel Corporation
- Yonggang Li
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Grid array connection device and method
- Patent number 9,966,351
- Issue date May 8, 2018
- Intel Corporation
- Munehiro Toyama
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit and process for fabricating thereof
- Patent number 9,941,158
- Issue date Apr 10, 2018
- Intel Corporation
- Charan Gurumurthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Grid array connection device and method
- Patent number 9,698,114
- Issue date Jul 4, 2017
- Intel Corporation
- Munehiro Toyama
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a substrate core structure using microvia laser d...
- Patent number 9,648,733
- Issue date May 9, 2017
- Intel Corporation
- Yonggang Li
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Panel with releasable core
- Patent number 9,554,472
- Issue date Jan 24, 2017
- Intel Corporation
- Ching-Ping Janet Shen
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Panel with releasable core
- Patent number 9,554,468
- Issue date Jan 24, 2017
- Intel Corporation
- Ching-Ping Janet Shen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Grid array connection device and method
- Patent number 9,449,936
- Issue date Sep 20, 2016
- Intel Corporation
- Munehiro Toyama
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Processes of making pad-less interconnect for electrical coreless s...
- Patent number 9,049,807
- Issue date Jun 2, 2015
- Intel Corporation
- Javier Soto
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method of forming a multilayer substrate core structure using seque...
- Patent number 8,877,565
- Issue date Nov 4, 2014
- Intel Corporation
- Yonggang Li
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method and core materials for semiconductor packaging
- Patent number 8,456,016
- Issue date Jun 4, 2013
- Intel Corporation
- Yonggang Li
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method of forming a substrate core structure using microvia laser d...
- Patent number 8,440,916
- Issue date May 14, 2013
- Intel Corporation
- Yonggang Li
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Doping of lead-free solder alloys and structures formed thereby
- Patent number 8,395,051
- Issue date Mar 12, 2013
- Intel Corporation
- Mengzhi Pang
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method of making substrate package with through holes for high spee...
- Patent number 8,353,101
- Issue date Jan 15, 2013
- Intel Corporation
- Charan Gurumurthy
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Embedding device in substrate cavity
- Patent number 8,115,307
- Issue date Feb 14, 2012
- Intel Corporation
- Munehiro Toyama
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Integrated circuit and process for fabricating thereof
- Patent number 7,998,857
- Issue date Aug 16, 2011
- Intel Corporation
- Charan Gurumurthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming collapse chip connection bumps on a semiconductor...
- Patent number 7,985,622
- Issue date Jul 26, 2011
- Intel Corporation
- Ravi Nalla
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Forming a helical inductor
- Patent number 7,956,713
- Issue date Jun 7, 2011
- Intel Corporation
- Arun Chandrasekhar
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Grid array connection device and method
- Patent number 7,915,060
- Issue date Mar 29, 2011
- Intel Corporation
- Munehiro Toyama
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Substrate package with through holes for high speed I/O flex cable
- Patent number 7,888,784
- Issue date Feb 15, 2011
- Intel Corporation
- Charan Gurumurthy
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Optical die structures and associated package substrates
- Patent number 7,831,115
- Issue date Nov 9, 2010
- Intel Corporation
- Omar Bchir
- G02 - OPTICS
Information Patent Grant
System, apparatus, and method for advanced solder bumping
- Patent number 7,790,598
- Issue date Sep 7, 2010
- Intel Corporation
- Mengzhi Pang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method and core materials for semiconductor packaging
- Patent number 7,749,900
- Issue date Jul 6, 2010
- Intel Corporation
- Yonggang Li
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Grid array connection device and method
- Patent number 7,670,951
- Issue date Mar 2, 2010
- Intel Corporation
- Munehiro Toyama
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Assembly of thin die coreless package
- Patent number 7,666,714
- Issue date Feb 23, 2010
- Intel Corporation
- Daoqiang Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Embedding device in substrate cavity
- Patent number 7,592,202
- Issue date Sep 22, 2009
- Intel Corporation
- Munehiro Toyama
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Substrates for optical die structures
- Patent number 7,583,871
- Issue date Sep 1, 2009
- Omar J. Bchir
- G02 - OPTICS
Information Patent Grant
System, apparatus, and method for advanced solder bumping
- Patent number 7,517,788
- Issue date Apr 14, 2009
- Intel Corporation
- Mengzhi Pang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method of forming through-silicon vias with stress buffer collars a...
- Patent number 7,402,515
- Issue date Jul 22, 2008
- Intel Corporation
- Leonel R. Arana
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package with low modulus layer and capacitor/int...
- Patent number 7,042,077
- Issue date May 9, 2006
- Intel Corporation
- Michael J. Walk
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
METHOD OF FORMING A SUBSTRATE CORE STRUCTURE USING MICROVIA LASER D...
- Publication number 20170231092
- Publication date Aug 10, 2017
- Intel Corporation
- Yonggang Li
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
PANEL WITH RELEASABLE CORE
- Publication number 20170202080
- Publication date Jul 13, 2017
- Intel Corporation
- Ching-Ping Janet Shen
- B32 - LAYERED PRODUCTS
Information Patent Application
GRID ARRAY CONNECTION DEVICE AND METHOD
- Publication number 20160365325
- Publication date Dec 15, 2016
- Intel Corporation
- Munehiro Toyama
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GRID ARRAY CONNECTION DEVICE AND METHOD
- Publication number 20150179600
- Publication date Jun 25, 2015
- Munehiro Toyama
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PANEL WITH RELEASABLE CORE
- Publication number 20150181717
- Publication date Jun 25, 2015
- Ching-Ping Janet Shen
- B32 - LAYERED PRODUCTS
Information Patent Application
PANEL WITH RELEASABLE CORE
- Publication number 20150181713
- Publication date Jun 25, 2015
- Ching-Ping Janet Shen
- B32 - LAYERED PRODUCTS
Information Patent Application
METHOD OF FORMING A SUBSTRATE CORE STRUCTURE USING MICROVIA LASER D...
- Publication number 20130242498
- Publication date Sep 19, 2013
- Yonggang Li
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
INTEGRATED CIRCUIT AND PROCESS FOR FABRICATING THEREOF
- Publication number 20110298135
- Publication date Dec 8, 2011
- Charan Gurumurthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOLDER JOINTS WITH ENHANCED ELECTROMIGRATION RESISTANCE
- Publication number 20110290864
- Publication date Dec 1, 2011
- Mengzhi PANG
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
SOLDER JOINTS WITH ENHANCED ELECTROMIGRATION RESISTANCE
- Publication number 20110293962
- Publication date Dec 1, 2011
- Mengzhi PANG
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
GRID ARRAY CONNECTION DEVICE AND METHOD
- Publication number 20110169167
- Publication date Jul 14, 2011
- Munehiro Toyama
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
SUBSTRATE PACKAGE WITH THROUGH HOLES FOR HIGH SPEED I/O FLEX CABLE
- Publication number 20110108427
- Publication date May 12, 2011
- Charan Gurumurthy
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
METHOD OF FORMING A MULTILAYER SUBSTRATE CORE STRUCTURE USING SEQUE...
- Publication number 20110058340
- Publication date Mar 10, 2011
- Yonggang Li
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
LGA SUBSTRATE AND METHOD OF MAKING SAME
- Publication number 20100301484
- Publication date Dec 2, 2010
- Omar J. Bchir
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
METHOD AND CORE MATERIALS FOR SEMICONDUCTOR PACKAGING
- Publication number 20100289154
- Publication date Nov 18, 2010
- Yonggang Li
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Doping of lead-free solder alloys and structures formed thereby
- Publication number 20100155115
- Publication date Jun 24, 2010
- Mengzhi Pang
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
SOLDER JOINTS WITH ENHANCED ELECTROMIGRATION RESISTANCE
- Publication number 20100155947
- Publication date Jun 24, 2010
- Mengzhi PANG
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
GRID ARRAY CONNECTION DEVICE AND METHOD
- Publication number 20100148365
- Publication date Jun 17, 2010
- Munehiro Toyama
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
METHOD AND CORE MATERIALS FOR SEMICONDUCTOR PACKAGING
- Publication number 20100078805
- Publication date Apr 1, 2010
- Yonggang Li
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
SUBSTRATE PACKAGE WITH THROUGH HOLES FOR HIGH SPEED I/O FLEX CABLE
- Publication number 20100078826
- Publication date Apr 1, 2010
- Charan Gurumurthy
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
METHOD OF FORMING COLLAPSE CHIP CONNECTION BUMPS ON A SEMICONDUCTOR...
- Publication number 20100044862
- Publication date Feb 25, 2010
- Ravi Nalla
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Direct layer laser lamination for electrical bump substrates, and p...
- Publication number 20090314519
- Publication date Dec 24, 2009
- Javier Soto
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
EMBEDDING DEVICE IN SUBSTRATE CAVITY
- Publication number 20090294992
- Publication date Dec 3, 2009
- Intel Corporation
- Munehiro Toyama
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
METHOD AND APPARATUS TO REDUCE PIN VOIDS
- Publication number 20090250824
- Publication date Oct 8, 2009
- Xiwang Qi
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
SUBSTRATES FOR OPTICAL DIE STRUCTURES
- Publication number 20090238516
- Publication date Sep 24, 2009
- Omar J. Bchir
- G02 - OPTICS
Information Patent Application
OPTICAL DIE STRUCTURES AND ASSOCIATED PACKAGE SUBSTRATES
- Publication number 20090238233
- Publication date Sep 24, 2009
- Omar Bchir
- G02 - OPTICS
Information Patent Application
SYSTEM, APPARATUS, AND METHOD FOR ADVANCED SOLDER BUMPING
- Publication number 20090196000
- Publication date Aug 6, 2009
- Mengzhi Pang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
LGA SUBSTRATE AND METHOD OF MAKING SAME
- Publication number 20090166858
- Publication date Jul 2, 2009
- Omar J. Bchir
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
INTEGRATED CIRCUIT AND PROCESS FOR FABRICATING THEREOF
- Publication number 20090108455
- Publication date Apr 30, 2009
- Intel Corporation
- Charan Gurumurthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Forming a helical inductor
- Publication number 20090079530
- Publication date Mar 26, 2009
- Arun Chandrasekhar
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Charan Gurumurthy

Person

Patents Grantslast 30 patents

Method of forming a substrate core structure using microvia laser d...

Grid array connection device and method

Integrated circuit and process for fabricating thereof

Grid array connection device and method

Method of forming a substrate core structure using microvia laser d...

Panel with releasable core

Panel with releasable core

Grid array connection device and method

Processes of making pad-less interconnect for electrical coreless s...

Method of forming a multilayer substrate core structure using seque...

Method and core materials for semiconductor packaging

Method of forming a substrate core structure using microvia laser d...

Doping of lead-free solder alloys and structures formed thereby

Method of making substrate package with through holes for high spee...

Embedding device in substrate cavity

Integrated circuit and process for fabricating thereof

Method of forming collapse chip connection bumps on a semiconductor...

Forming a helical inductor

Grid array connection device and method

Substrate package with through holes for high speed I/O flex cable

Optical die structures and associated package substrates

System, apparatus, and method for advanced solder bumping

Method and core materials for semiconductor packaging

Grid array connection device and method

Assembly of thin die coreless package

Embedding device in substrate cavity

Substrates for optical die structures

System, apparatus, and method for advanced solder bumping

Method of forming through-silicon vias with stress buffer collars a...

Integrated circuit package with low modulus layer and capacitor/int...

Patents Applicationslast 30 patents

METHOD OF FORMING A SUBSTRATE CORE STRUCTURE USING MICROVIA LASER D...

PANEL WITH RELEASABLE CORE

GRID ARRAY CONNECTION DEVICE AND METHOD

GRID ARRAY CONNECTION DEVICE AND METHOD

PANEL WITH RELEASABLE CORE

PANEL WITH RELEASABLE CORE

METHOD OF FORMING A SUBSTRATE CORE STRUCTURE USING MICROVIA LASER D...

INTEGRATED CIRCUIT AND PROCESS FOR FABRICATING THEREOF

SOLDER JOINTS WITH ENHANCED ELECTROMIGRATION RESISTANCE

SOLDER JOINTS WITH ENHANCED ELECTROMIGRATION RESISTANCE

GRID ARRAY CONNECTION DEVICE AND METHOD

SUBSTRATE PACKAGE WITH THROUGH HOLES FOR HIGH SPEED I/O FLEX CABLE

METHOD OF FORMING A MULTILAYER SUBSTRATE CORE STRUCTURE USING SEQUE...

LGA SUBSTRATE AND METHOD OF MAKING SAME

METHOD AND CORE MATERIALS FOR SEMICONDUCTOR PACKAGING

Doping of lead-free solder alloys and structures formed thereby

SOLDER JOINTS WITH ENHANCED ELECTROMIGRATION RESISTANCE

GRID ARRAY CONNECTION DEVICE AND METHOD

METHOD AND CORE MATERIALS FOR SEMICONDUCTOR PACKAGING

SUBSTRATE PACKAGE WITH THROUGH HOLES FOR HIGH SPEED I/O FLEX CABLE

METHOD OF FORMING COLLAPSE CHIP CONNECTION BUMPS ON A SEMICONDUCTOR...

Direct layer laser lamination for electrical bump substrates, and p...

EMBEDDING DEVICE IN SUBSTRATE CAVITY

METHOD AND APPARATUS TO REDUCE PIN VOIDS

SUBSTRATES FOR OPTICAL DIE STRUCTURES

OPTICAL DIE STRUCTURES AND ASSOCIATED PACKAGE SUBSTRATES

SYSTEM, APPARATUS, AND METHOD FOR ADVANCED SOLDER BUMPING

LGA SUBSTRATE AND METHOD OF MAKING SAME

INTEGRATED CIRCUIT AND PROCESS FOR FABRICATING THEREOF

Forming a helical inductor