Charles D. Wait

Person

Byron, MN, US

People

Patents Grantslast 30 patents

Information Patent Grant
Unified translation miss queue for multiple address translation modes
- Patent number 11,734,188
- Issue date Aug 22, 2023
- International Business Machines Corporation
- Charles D. Wait
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sleeping and waking-up address translation that conflicts with tran...
- Patent number 11,636,043
- Issue date Apr 25, 2023
- International Business Machines Corporation
- Charles D. Wait
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Determining page size via page table cache
- Patent number 11,422,947
- Issue date Aug 23, 2022
- International Business Machines Corporation
- David Campbell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Promotion of ERAT cache entries
- Patent number 11,221,957
- Issue date Jan 11, 2022
- International Business Machines Corporation
- Bartholomew Blaner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing translation latency within a memory management unit using...
- Patent number 10,671,537
- Issue date Jun 2, 2020
- International Business Machines Corporation
- Guy L. Guthrie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing translation latency within a memory management unit using...
- Patent number 10,649,902
- Issue date May 12, 2020
- International Business Machines Corporation
- Guy L. Guthrie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Ensuring forward progress for nested translations in a memory manag...
- Patent number 10,380,031
- Issue date Aug 13, 2019
- International Business Machines Corporation
- Guy L. Guthrie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Ensuring forward progress for nested translations in a memory manag...
- Patent number 10,318,435
- Issue date Jun 11, 2019
- International Business Machines Corporation
- Guy L. Guthrie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction predication using instruction address pattern matching
- Patent number 10,261,793
- Issue date Apr 16, 2019
- International Business Machines Corporation
- Mark J Hickey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Branch prediction with power usage prediction and control
- Patent number 10,067,556
- Issue date Sep 4, 2018
- International Business Machines Corporation
- Mark J Hickey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Branch prediction with power usage prediction and control
- Patent number 10,042,417
- Issue date Aug 7, 2018
- International Business Machines Corporation
- Mark J Hickey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-petascale highly efficient parallel supercomputer
- Patent number 9,971,713
- Issue date May 15, 2018
- GLOBALFOUNDRIES Inc.
- Sameh Asaad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Branch prediction with power usage prediction and control
- Patent number 9,395,804
- Issue date Jul 19, 2016
- International Business Machines Corporation
- Mark J Hickey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic range adjusting floating point execution unit
- Patent number 9,223,753
- Issue date Dec 29, 2015
- International Business Machines Corporation
- Mark J Hickey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing core with speculative register preprocessing in unused e...
- Patent number 9,195,463
- Issue date Nov 24, 2015
- International Business Machines Corporation
- Mark J Hickey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-petascale highly efficient parallel supercomputer
- Patent number 9,081,501
- Issue date Jul 14, 2015
- International Business Machines Corporation
- Sameh Asaad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Opcode space minimizing architecture utilizing a least significant...
- Patent number 9,075,599
- Issue date Jul 7, 2015
- International Business Machines Corporation
- Mark J Hickey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Floating point execution unit with fixed point functionality
- Patent number 8,930,432
- Issue date Jan 6, 2015
- International Business Machines Corporation
- Mark J Hickey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Detecting logically non-significant operation based on opcode and o...
- Patent number 8,880,852
- Issue date Nov 4, 2014
- International Business Machines Corporation
- Mark J Hickey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fault tolerant stability critical execution checking using redundan...
- Patent number 8,707,094
- Issue date Apr 22, 2014
- International Business Machines Corporation
- Mark J Hickey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performing vector multiplication
- Patent number 8,629,867
- Issue date Jan 14, 2014
- International Business Machines Corporation
- Mark J Hickey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register file soft error recovery
- Patent number 8,560,924
- Issue date Oct 15, 2013
- International Business Machines Corporation
- Bruce M. Fleischer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable integrated processor blocks
- Patent number 8,522,254
- Issue date Aug 27, 2013
- International Business Machines Corporation
- Mark J. Hickey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic range adjusting floating point execution unit
- Patent number 8,412,760
- Issue date Apr 2, 2013
- International Business Machines Corporation
- Mark J Hickey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fault tolerant stability critical execution checking using redundan...
- Patent number 8,412,980
- Issue date Apr 2, 2013
- International Business Machines Corporation
- Mark J Hickey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic merging of pipeline stages in an execution pipeline to redu...
- Patent number 8,291,201
- Issue date Oct 16, 2012
- International Business Machines Corporation
- Stephen Joseph Schwinn
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Implied storage operation decode using redundant target address det...
- Patent number 8,255,674
- Issue date Aug 28, 2012
- International Business Machines Corporation
- Mark Joseph Hickey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structural power reduction in multithreaded processor
- Patent number 8,140,830
- Issue date Mar 20, 2012
- International Business Machines Corporation
- Stephen Joseph Schwinn
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Data dependent instruction decode
- Patent number 8,028,153
- Issue date Sep 27, 2011
- International Business Machines Corporation
- Mark J Hickey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Redundant execution of instructions in multistage execution pipelin...
- Patent number 7,975,172
- Issue date Jul 5, 2011
- International Business Machines Corporation
- Mark J Hickey
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SLEEP / WAKE-UP PERFORMANCE ENHANCING FOR SIMULTANEOUS ADDRESS TRAN...
- Publication number 20230062909
- Publication date Mar 2, 2023
- International Business Machines Corporation
- Charles D. Wait
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UNIFIED TRANSLATION MISS QUEUE FOR MULTIPLE ADDRESS TRANSLATION MODES
- Publication number 20220292028
- Publication date Sep 15, 2022
- International Business Machines Corporation
- Charles D. Wait
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DETERMINING PAGE SIZE VIA PAGE TABLE CACHE
- Publication number 20220050792
- Publication date Feb 17, 2022
- International Business Machines Corporation
- David Campbell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROMOTION OF ERAT CACHE ENTRIES
- Publication number 20200073817
- Publication date Mar 5, 2020
- International Business Machines Corporation
- Bartholomew Blaner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCING TRANSLATION LATENCY WITHIN A MEMORY MANAGEMENT UNIT USING...
- Publication number 20190065380
- Publication date Feb 28, 2019
- International Business Machines Corporation
- GUY L. GUTHRIE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENSURING FORWARD PROGRESS FOR NESTED TRANSLATIONS IN A MEMORY MANAG...
- Publication number 20190065398
- Publication date Feb 28, 2019
- International Business Machines Corporation
- GUY L. GUTHRIE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCING TRANSLATION LATENCY WITHIN A MEMORY MANAGEMENT UNIT USING...
- Publication number 20190065379
- Publication date Feb 28, 2019
- International Business Machines Corporation
- GUY L. GUTHRIE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENSURING FORWARD PROGRESS FOR NESTED TRANSLATIONS IN A MEMORY MANAG...
- Publication number 20190065399
- Publication date Feb 28, 2019
- International Business Machines Corporation
- GUY L. GUTHRIE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MAINTAINING AGENT INCLUSIVITY WITHIN A DISTRIBUTED MMU
- Publication number 20180300256
- Publication date Oct 18, 2018
- International Business Machines Corporation
- BARTHOLOMEW BLANER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MAINTAINING AGENT INCLUSIVITY WITHIN A DISTRIBUTED MMU
- Publication number 20180300255
- Publication date Oct 18, 2018
- International Business Machines Corporation
- BARTHOLOMEW BLANER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BRANCH PREDICTION WITH POWER USAGE PREDICTION AND CONTROL
- Publication number 20160313788
- Publication date Oct 27, 2016
- International Business Machines Corporation
- Mark J. Hickey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER
- Publication number 20160011996
- Publication date Jan 14, 2016
- International Business Machines Corporation
- Sameh Asaad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BRANCH PREDICTION WITH POWER USAGE PREDICTION AND CONTROL
- Publication number 20150370308
- Publication date Dec 24, 2015
- International Business Machines Corporation
- Mark J. Hickey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BRANCH PREDICTION WITH POWER USAGE PREDICTION AND CONTROL
- Publication number 20140229720
- Publication date Aug 14, 2014
- International Business Machines Corporation
- Mark J. Hickey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC RANGE ADJUSTING FLOATING POINT EXECUTION UNIT
- Publication number 20130191432
- Publication date Jul 25, 2013
- International Business Machines Corporation
- Mark J. Hickey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAULT TOLERANT STABILITY CRITICAL EXECUTION CHECKING USING REDUNDAN...
- Publication number 20130185604
- Publication date Jul 18, 2013
- International Business Machines Corporation
- Mark J. Hickey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION PREDICATION USING INSTRUCTION ADDRESS PATTERN MATCHING
- Publication number 20130159683
- Publication date Jun 20, 2013
- International Business Machines Corporation
- Mark J. Hickey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSING CORE WITH SPECULATIVE REGISTER PREPROCESSING
- Publication number 20130138925
- Publication date May 30, 2013
- International Business Machines Corporation
- Mark J. Hickey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION ADDRESS ADJUSTMENT IN RESPONSE TO LOGICALLY NON-SIGNIFI...
- Publication number 20130111186
- Publication date May 2, 2013
- International Business Machines Corporation
- Mark J. Hickey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLOATING POINT EXECUTION UNIT WITH FIXED POINT FUNCTIONALITY
- Publication number 20130036296
- Publication date Feb 7, 2013
- International Business Machines Corporation
- Mark J. Hickey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Opcode Space Minimizing Architecture Utilizing Instruction Address...
- Publication number 20120084535
- Publication date Apr 5, 2012
- International Business Machines Corporation
- Mark J. Hickey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable Integrated Processor Blocks
- Publication number 20110321049
- Publication date Dec 29, 2011
- International Business Machines Corporation
- Mark J. Hickey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAULT TOLERANT STABILITY CRITICAL EXECUTION CHECKING USING REDUNDAN...
- Publication number 20110302450
- Publication date Dec 8, 2011
- International Business Machines Corporation
- Mark J. Hickey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERFORMING VECTOR MULTIPLICATION
- Publication number 20110298788
- Publication date Dec 8, 2011
- International Business Machines Corporation
- Mark J. Hickey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER
- Publication number 20110219208
- Publication date Sep 8, 2011
- International Business Machines Corporation
- Sameh Asaad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REGISTER FILE SOFT ERROR RECOVERY
- Publication number 20110167296
- Publication date Jul 7, 2011
- International Business Machines Corporation
- Thomas W. Fox
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Implied Storage Operation Decode Using Redundant Target Address Det...
- Publication number 20100191937
- Publication date Jul 29, 2010
- International Business Machines Corporation
- Mark Joseph Hickey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multithreaded Processing Unit With Thread Pair Context Caching
- Publication number 20100125722
- Publication date May 20, 2010
- International Business Machines Corporation
- Mark J. Hickey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instruction Target History Based Register Address Indexing
- Publication number 20100125719
- Publication date May 20, 2010
- International Business Machines Corporation
- Mark Joseph Hickey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Redundant Execution of Instructions in Multistage Execution Pipelin...
- Publication number 20100042813
- Publication date Feb 18, 2010
- International Business Machines Corporation
- Mark J. Hickey
- G06 - COMPUTING CALCULATING COUNTING

Charles D. Wait

Person

Patents Grantslast 30 patents

Unified translation miss queue for multiple address translation modes

Sleeping and waking-up address translation that conflicts with tran...

Determining page size via page table cache

Promotion of ERAT cache entries

Reducing translation latency within a memory management unit using...

Reducing translation latency within a memory management unit using...

Ensuring forward progress for nested translations in a memory manag...

Ensuring forward progress for nested translations in a memory manag...

Instruction predication using instruction address pattern matching

Branch prediction with power usage prediction and control

Branch prediction with power usage prediction and control

Multi-petascale highly efficient parallel supercomputer

Branch prediction with power usage prediction and control

Dynamic range adjusting floating point execution unit

Processing core with speculative register preprocessing in unused e...

Multi-petascale highly efficient parallel supercomputer

Opcode space minimizing architecture utilizing a least significant...

Floating point execution unit with fixed point functionality

Detecting logically non-significant operation based on opcode and o...

Fault tolerant stability critical execution checking using redundan...

Performing vector multiplication

Register file soft error recovery

Programmable integrated processor blocks

Dynamic range adjusting floating point execution unit

Fault tolerant stability critical execution checking using redundan...

Dynamic merging of pipeline stages in an execution pipeline to redu...

Implied storage operation decode using redundant target address det...

Structural power reduction in multithreaded processor

Data dependent instruction decode

Redundant execution of instructions in multistage execution pipelin...

Patents Applicationslast 30 patents

SLEEP / WAKE-UP PERFORMANCE ENHANCING FOR SIMULTANEOUS ADDRESS TRAN...

UNIFIED TRANSLATION MISS QUEUE FOR MULTIPLE ADDRESS TRANSLATION MODES

DETERMINING PAGE SIZE VIA PAGE TABLE CACHE

PROMOTION OF ERAT CACHE ENTRIES

REDUCING TRANSLATION LATENCY WITHIN A MEMORY MANAGEMENT UNIT USING...

ENSURING FORWARD PROGRESS FOR NESTED TRANSLATIONS IN A MEMORY MANAG...

REDUCING TRANSLATION LATENCY WITHIN A MEMORY MANAGEMENT UNIT USING...

ENSURING FORWARD PROGRESS FOR NESTED TRANSLATIONS IN A MEMORY MANAG...

MAINTAINING AGENT INCLUSIVITY WITHIN A DISTRIBUTED MMU

MAINTAINING AGENT INCLUSIVITY WITHIN A DISTRIBUTED MMU

BRANCH PREDICTION WITH POWER USAGE PREDICTION AND CONTROL

MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER

BRANCH PREDICTION WITH POWER USAGE PREDICTION AND CONTROL

BRANCH PREDICTION WITH POWER USAGE PREDICTION AND CONTROL

DYNAMIC RANGE ADJUSTING FLOATING POINT EXECUTION UNIT

FAULT TOLERANT STABILITY CRITICAL EXECUTION CHECKING USING REDUNDAN...

INSTRUCTION PREDICATION USING INSTRUCTION ADDRESS PATTERN MATCHING

PROCESSING CORE WITH SPECULATIVE REGISTER PREPROCESSING

INSTRUCTION ADDRESS ADJUSTMENT IN RESPONSE TO LOGICALLY NON-SIGNIFI...

FLOATING POINT EXECUTION UNIT WITH FIXED POINT FUNCTIONALITY

Opcode Space Minimizing Architecture Utilizing Instruction Address...

Programmable Integrated Processor Blocks

FAULT TOLERANT STABILITY CRITICAL EXECUTION CHECKING USING REDUNDAN...

PERFORMING VECTOR MULTIPLICATION

MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER

REGISTER FILE SOFT ERROR RECOVERY

Implied Storage Operation Decode Using Redundant Target Address Det...

Multithreaded Processing Unit With Thread Pair Context Caching

Instruction Target History Based Register Address Indexing

Redundant Execution of Instructions in Multistage Execution Pipelin...