Charles H. Wallace

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Advanced lithography and self-assembled devices
- Patent number 12,218,052
- Issue date Feb 4, 2025
- Intel Corporation
- Richard E. Schenker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Contact over active gate structures with tapered gate or trench con...
- Patent number 12,199,161
- Issue date Jan 14, 2025
- Intel Corporation
- Charles H. Wallace
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned patterning with colored blocking and structures result...
- Patent number 12,154,855
- Issue date Nov 26, 2024
- Intel Corporation
- Mohit K. Haran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self aligned gratings for tight pitch interconnects and methods of...
- Patent number 12,131,991
- Issue date Oct 29, 2024
- Intel Corporation
- Manish Chandhok
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical metal splitting using helmets and wrap-around dielectric s...
- Patent number 12,131,989
- Issue date Oct 29, 2024
- Intel Corporation
- Leonard P. Guler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Metal oxycarbide resists as leave behind plugs
- Patent number 12,107,044
- Issue date Oct 1, 2024
- Intel Corporation
- Marie Krysak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Colored gratings in microelectronic structures
- Patent number 12,087,594
- Issue date Sep 10, 2024
- Intel Corporation
- Gurpreet Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Contact over active gate structures with metal oxide layers to inhi...
- Patent number 12,080,639
- Issue date Sep 3, 2024
- Intel Corporation
- Rami Hourani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication of gate-all-around integrated circuit structures having...
- Patent number 12,068,314
- Issue date Aug 20, 2024
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Enhanced grating aligned patterning for EUV direct print processes
- Patent number 12,051,623
- Issue date Jul 30, 2024
- Intel Corporation
- Seyedhamed M Barghi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate aligned contact and method to fabricate same
- Patent number 12,033,894
- Issue date Jul 9, 2024
- Intel Corporation
- Oleg Golonzka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate spacing in integrated circuit structures
- Patent number 12,002,678
- Issue date Jun 4, 2024
- Intel Corporation
- Charles Henry Wallace
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
1D vertical edge blocking (VEB) via and plug
- Patent number 11,972,979
- Issue date Apr 30, 2024
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Advanced lithography and self-assembled devices
- Patent number 11,854,787
- Issue date Dec 26, 2023
- Intel Corporation
- Richard E. Schenker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate aligned contact and method to fabricate same
- Patent number 11,756,829
- Issue date Sep 12, 2023
- Intel Corporation
- Oleg Golonzka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
1D vertical edge blocking (VEB) via and plug
- Patent number 11,721,580
- Issue date Aug 8, 2023
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal and spacer patterning for pitch division with multiple line w...
- Patent number 11,710,636
- Issue date Jul 25, 2023
- Intel Corporation
- Kevin Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to repair edge placement errors in a semiconductor device
- Patent number 11,664,274
- Issue date May 30, 2023
- Intel Corporation
- Charles H. Wallace
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Via contact patterning method to increase edge placement error margin
- Patent number 11,652,045
- Issue date May 16, 2023
- Intel Corporation
- Mohit K. Haran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical edge blocking (VEB) technique for increasing patterning pr...
- Patent number 11,594,448
- Issue date Feb 28, 2023
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Via and plug architectures for integrated circuit interconnects and...
- Patent number 11,527,433
- Issue date Dec 13, 2022
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate aligned contact and method to fabricate same
- Patent number 11,495,496
- Issue date Nov 8, 2022
- Intel Corporation
- Oleg Golonzka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fuse lines and plugs for semiconductor devices
- Patent number 11,476,190
- Issue date Oct 18, 2022
- Intel Corporation
- Balijeet S. Bains
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Conductive cap-based approaches for conductive via fabrication and...
- Patent number 11,417,567
- Issue date Aug 16, 2022
- Intel Corporation
- Florian Gstrein
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Advanced lithography and self-assembled devices
- Patent number 11,373,950
- Issue date Jun 28, 2022
- Intel Corporation
- Richard E. Schenker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self aligned gratings for tight pitch interconnects and methods of...
- Patent number 11,251,117
- Issue date Feb 15, 2022
- Intel Corporation
- Manish Chandhok
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Via contact patterning method to increase edge placement error margin
- Patent number 11,211,324
- Issue date Dec 28, 2021
- Intel Corporation
- Mohit K. Haran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Plug and trench architectures for integrated circuits and methods o...
- Patent number 11,171,043
- Issue date Nov 9, 2021
- Intel Corporation
- Charles H. Wallace
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Conductive via and metal line end fabrication and structures result...
- Patent number 11,145,541
- Issue date Oct 12, 2021
- Intel Corporation
- Charles H. Wallace
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pattern decomposition lithography techniques
- Patent number 11,107,786
- Issue date Aug 31, 2021
- Intel Corporation
- Charles H. Wallace
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SELF-ALIGNED PATTERNING WITH COLORED BLOCKING AND STRUCTURES RESULT...
- Publication number 20250046713
- Publication date Feb 6, 2025
- Intel Corporation
- Mohit K. HARAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICAL METAL SPLITTING USING HELMETS AND WRAP-AROUND DIELECTRIC S...
- Publication number 20250029915
- Publication date Jan 23, 2025
- Intel Corporation
- Leonard P. Guler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT STRUCTURE WITH BACKSIDE SOURCE OR DRAIN CONTACT...
- Publication number 20250006740
- Publication date Jan 2, 2025
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING REDUCED END CAP
- Publication number 20250006787
- Publication date Jan 2, 2025
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES WITH INTERNAL SPACER LINERS
- Publication number 20250006808
- Publication date Jan 2, 2025
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONDUCTIVE LINES HAVING CONDUCTIVE METAL LINER FOR ADVANCED INTEGRA...
- Publication number 20250006628
- Publication date Jan 2, 2025
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURE WITH DEEP VIA BAR ISOLATION
- Publication number 20240429125
- Publication date Dec 26, 2024
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRENCH CONNECTION OVER DISCONNECTED EPITAXIAL STRUCTURE USING DIREC...
- Publication number 20240421201
- Publication date Dec 19, 2024
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES WITH PARTIAL CHANNEL CAP REMOVAL
- Publication number 20240395886
- Publication date Nov 28, 2024
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING...
- Publication number 20240363628
- Publication date Oct 31, 2024
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BACKSIDE CONDUCTIVE STRUCTURES EXTENDING THROUGH INTEGRATED CIRCUIT...
- Publication number 20240355915
- Publication date Oct 24, 2024
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONDUCTIVE BRIDGE THROUGH DIELECTRIC WALL BETWEEN SOURCE OR DRAIN C...
- Publication number 20240355890
- Publication date Oct 24, 2024
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONDUCTIVE BRIDGE THROUGH DIELECTRIC WALL BETWEEN SOURCE OR DRAIN C...
- Publication number 20240355891
- Publication date Oct 24, 2024
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR WITH CHANNEL-SYMMETRIC GATE
- Publication number 20240332290
- Publication date Oct 3, 2024
- Intel Corporation
- Shao-Ming Koh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONSTRAINED EPITAXIAL FORMATION USING DIELECTRIC WALLS
- Publication number 20240321892
- Publication date Sep 26, 2024
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICES BETWEEN GATE CUTS AND DEEP BACKSIDE VIAS
- Publication number 20240321685
- Publication date Sep 26, 2024
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ISOLATED BACKSIDE CONTACTS FOR SEMICONDUCTOR DEVICES
- Publication number 20240321737
- Publication date Sep 26, 2024
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BRIDGING CONTACT STRUCTURES
- Publication number 20240321738
- Publication date Sep 26, 2024
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONTACT EXTENDED OVER AN ADJACENT SOURCE OR DRAIN REGION
- Publication number 20240321978
- Publication date Sep 26, 2024
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE ALIGNED CONTACT AND METHOD TO FABRICATE SAME
- Publication number 20240282633
- Publication date Aug 22, 2024
- Intel Corporation
- Oleg GOLONZKA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE SPACING IN INTEGRATED CIRCUIT STRUCTURES
- Publication number 20240249946
- Publication date Jul 25, 2024
- Intel Corporation
- Charles Henry Wallace
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND APPARATUS TO REDUCE EXTREME ULTRAVIOLET LIGHT FOR PHOTO...
- Publication number 20240241446
- Publication date Jul 18, 2024
- Intel Corporation
- Marvin Paik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED BACKBONE FOR FORKSHEET TRANSISTORS
- Publication number 20240213250
- Publication date Jun 27, 2024
- Intel Corporation
- Shao Ming KOH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DSA (DIRECTED SELF-ASSEMBLY) BASED SPACER AND LINER FOR SHORTING MA...
- Publication number 20240204083
- Publication date Jun 20, 2024
- Intel Corporation
- Gurpreet Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
High Density Transistor and Routing Track Architecture
- Publication number 20240202415
- Publication date Jun 20, 2024
- Intel Corporation
- Quan Shi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DEVICES WITH HYBRID METAL LINES
- Publication number 20240203869
- Publication date Jun 20, 2024
- Intel Corporation
- Sukru Yemenicioglu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING DIELECTRIC ANCHOR AND CONFINED...
- Publication number 20240154037
- Publication date May 9, 2024
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING DIELECTRIC ANCHOR VOID
- Publication number 20240145568
- Publication date May 2, 2024
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED SOURCE OR DRAIN CONTACT FLYOVER
- Publication number 20240113177
- Publication date Apr 4, 2024
- Intel Corporation
- Sukru Yemenicioglu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SPLIT VIA STRUCTURES COUPLED TO CONDUCTIVE LINES FOR ADVANCED INTEG...
- Publication number 20240113019
- Publication date Apr 4, 2024
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS

Charles H. Wallace

Person

Patents Grantslast 30 patents

Advanced lithography and self-assembled devices

Contact over active gate structures with tapered gate or trench con...

Self-aligned patterning with colored blocking and structures result...

Self aligned gratings for tight pitch interconnects and methods of...

Vertical metal splitting using helmets and wrap-around dielectric s...

Metal oxycarbide resists as leave behind plugs

Colored gratings in microelectronic structures

Contact over active gate structures with metal oxide layers to inhi...

Fabrication of gate-all-around integrated circuit structures having...

Enhanced grating aligned patterning for EUV direct print processes

Gate aligned contact and method to fabricate same

Gate spacing in integrated circuit structures

1D vertical edge blocking (VEB) via and plug

Advanced lithography and self-assembled devices

Gate aligned contact and method to fabricate same

1D vertical edge blocking (VEB) via and plug

Metal and spacer patterning for pitch division with multiple line w...

Method to repair edge placement errors in a semiconductor device

Via contact patterning method to increase edge placement error margin

Vertical edge blocking (VEB) technique for increasing patterning pr...

Via and plug architectures for integrated circuit interconnects and...

Gate aligned contact and method to fabricate same

Fuse lines and plugs for semiconductor devices

Conductive cap-based approaches for conductive via fabrication and...

Advanced lithography and self-assembled devices

Self aligned gratings for tight pitch interconnects and methods of...

Via contact patterning method to increase edge placement error margin

Plug and trench architectures for integrated circuits and methods o...

Conductive via and metal line end fabrication and structures result...

Pattern decomposition lithography techniques

Patents Applicationslast 30 patents

SELF-ALIGNED PATTERNING WITH COLORED BLOCKING AND STRUCTURES RESULT...

VERTICAL METAL SPLITTING USING HELMETS AND WRAP-AROUND DIELECTRIC S...

INTEGRATED CIRCUIT STRUCTURE WITH BACKSIDE SOURCE OR DRAIN CONTACT...

INTEGRATED CIRCUIT STRUCTURES HAVING REDUCED END CAP

INTEGRATED CIRCUIT STRUCTURES WITH INTERNAL SPACER LINERS

CONDUCTIVE LINES HAVING CONDUCTIVE METAL LINER FOR ADVANCED INTEGRA...

INTEGRATED CIRCUIT STRUCTURE WITH DEEP VIA BAR ISOLATION

TRENCH CONNECTION OVER DISCONNECTED EPITAXIAL STRUCTURE USING DIREC...

INTEGRATED CIRCUIT STRUCTURES WITH PARTIAL CHANNEL CAP REMOVAL

FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING...

BACKSIDE CONDUCTIVE STRUCTURES EXTENDING THROUGH INTEGRATED CIRCUIT...

CONDUCTIVE BRIDGE THROUGH DIELECTRIC WALL BETWEEN SOURCE OR DRAIN C...

CONDUCTIVE BRIDGE THROUGH DIELECTRIC WALL BETWEEN SOURCE OR DRAIN C...

TRANSISTOR WITH CHANNEL-SYMMETRIC GATE

CONSTRAINED EPITAXIAL FORMATION USING DIELECTRIC WALLS

SEMICONDUCTOR DEVICES BETWEEN GATE CUTS AND DEEP BACKSIDE VIAS

ISOLATED BACKSIDE CONTACTS FOR SEMICONDUCTOR DEVICES

BRIDGING CONTACT STRUCTURES

CONTACT EXTENDED OVER AN ADJACENT SOURCE OR DRAIN REGION

GATE ALIGNED CONTACT AND METHOD TO FABRICATE SAME

GATE SPACING IN INTEGRATED CIRCUIT STRUCTURES

METHODS AND APPARATUS TO REDUCE EXTREME ULTRAVIOLET LIGHT FOR PHOTO...

SELF-ALIGNED BACKBONE FOR FORKSHEET TRANSISTORS

DSA (DIRECTED SELF-ASSEMBLY) BASED SPACER AND LINER FOR SHORTING MA...

High Density Transistor and Routing Track Architecture

INTEGRATED CIRCUIT DEVICES WITH HYBRID METAL LINES

INTEGRATED CIRCUIT STRUCTURES HAVING DIELECTRIC ANCHOR AND CONFINED...

INTEGRATED CIRCUIT STRUCTURES HAVING DIELECTRIC ANCHOR VOID

STACKED SOURCE OR DRAIN CONTACT FLYOVER

SPLIT VIA STRUCTURES COUPLED TO CONDUCTIVE LINES FOR ADVANCED INTEG...