Charles J. Alpert

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Post-CTS insertion delay and skew target reformulation of clock tree
- Patent number 12,061,857
- Issue date Aug 13, 2024
- Cadence Design Systems, Inc.
- Andrew Mark Chapman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fault-tolerant power-driven synthesis
- Patent number 11,301,757
- Issue date Apr 12, 2022
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Waveform propagation timing modeling for circuit design
- Patent number 10,796,049
- Issue date Oct 6, 2020
- Cadence Design Systems, Inc.
- Kwangsoo Han
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power driven synaptic network synthesis
- Patent number 10,679,120
- Issue date Jun 9, 2020
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
View pruning for routing tree optimization
- Patent number 10,643,019
- Issue date May 5, 2020
- Cadence Design Systems, Inc.
- Kwangsoo Han
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for routing a clock net with multiple layer ranges
- Patent number 10,579,767
- Issue date Mar 3, 2020
- Cadence Design Systems, Inc.
- Zhuo Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fault-tolerant power-driven synthesis
- Patent number 10,552,740
- Issue date Feb 4, 2020
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing topology generation using spine-like tree structure
- Patent number 10,460,065
- Issue date Oct 29, 2019
- Cadence Design Systems, Inc.
- Wen-Hao Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Region aware clustering
- Patent number 10,402,522
- Issue date Sep 3, 2019
- Cadence Design Systems, Inc.
- Natarajan Viswanathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement of cells in a multi-level routing tree
- Patent number 10,402,533
- Issue date Sep 3, 2019
- Cadence Design Systems, Inc.
- William Robert Reece
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for modifying a balanced clock structure
- Patent number 10,380,287
- Issue date Aug 13, 2019
- Cadence Design Systems, Inc.
- Dirk Meyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power-driven synthesis under latency constraints
- Patent number 10,354,183
- Issue date Jul 16, 2019
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for clock tree generation with buffers and inve...
- Patent number 10,354,040
- Issue date Jul 16, 2019
- Cadence Design Systems, Inc.
- Amin Farshidi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Balanced scaled-load clustering
- Patent number 10,318,693
- Issue date Jun 11, 2019
- Cadence Design Systems, Inc.
- Natarajan Viswanathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Local cluster refinement
- Patent number 10,289,797
- Issue date May 14, 2019
- Cadence Design Systems, Inc.
- Natarajan Viswanathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing tree topology generation
- Patent number 10,289,795
- Issue date May 14, 2019
- Cadence Design Systems, Inc.
- Jhih-Rong Gao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for assigning clock taps based on timing
- Patent number 10,289,775
- Issue date May 14, 2019
- Cadence Design Systems, Inc.
- Brian Wilson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for clock tree clustering
- Patent number 10,282,506
- Issue date May 7, 2019
- Cadence Design Systems, Inc.
- Dirk Meyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for power efficient flop clustering
- Patent number 10,216,880
- Issue date Feb 26, 2019
- Cadence Design Systems, Inc.
- Wen-Hao Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock cell library selection
- Patent number 10,198,551
- Issue date Feb 5, 2019
- Cadence Design Systems, Inc.
- Amin Farshidi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for constructing spanning trees
- Patent number 10,102,328
- Issue date Oct 16, 2018
- Cadence Design Systems, Inc.
- Wen-Hao Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for symmetric H-tree construction with complica...
- Patent number 10,095,824
- Issue date Oct 9, 2018
- Cadence Design Systems, Inc.
- Zhuo Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for congestion and routability aware detailed p...
- Patent number 10,031,994
- Issue date Jul 24, 2018
- Cadence Design Systems, Inc.
- Wen Hao Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient Ceff model for gate output slew computation in early synt...
- Patent number 9,946,824
- Issue date Apr 17, 2018
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Addressing coupled noise-based violations with buffering in a batch...
- Patent number 9,875,326
- Issue date Jan 23, 2018
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for evaluating spanning trees
- Patent number 9,785,738
- Issue date Oct 10, 2017
- Cadence Design Systems, Inc.
- Charles Jay Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Element placement in circuit design based on preferred location
- Patent number 9,524,363
- Issue date Dec 20, 2016
- GLOBALFOUNDRIES Inc.
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Solving network traffic congestion using device grouping
- Patent number 9,106,560
- Issue date Aug 11, 2015
- International Business Machines Corporation
- Charles Jay Alpert
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Boundary latch and logic placement to satisfy timing constraints
- Patent number 9,098,669
- Issue date Aug 4, 2015
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic generation of wire tag lists for a metal stack
- Patent number 9,092,591
- Issue date Jul 28, 2015
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
FAULT-TOLERANT POWER-DRIVEN SYNTHESIS
- Publication number 20200097833
- Publication date Mar 26, 2020
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Addressing Coupled Noise-Based Violations with Buffering in a Batch...
- Publication number 20170161407
- Publication date Jun 8, 2017
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER DRIVEN SYNAPTIC NETWORK SYNTHESIS
- Publication number 20160132767
- Publication date May 12, 2016
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER-DRIVEN SYNTHESIS UNDER LATENCY CONSTRAINTS
- Publication number 20160132765
- Publication date May 12, 2016
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAULT-TOLERANT POWER-DRIVEN SYNTHESIS
- Publication number 20160132769
- Publication date May 12, 2016
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BOUNDARY LATCH AND LOGIC PLACEMENT TO SATISFY TIMING CONSTRAINTS
- Publication number 20150199465
- Publication date Jul 16, 2015
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT CEFF MODEL FOR GATE OUTPUT SLEW COMPUTATION IN EARLY SYNT...
- Publication number 20150143326
- Publication date May 21, 2015
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTER-BASED MODELING OF INTEGRATED CIRCUIT CONGESTION AND WIRE D...
- Publication number 20150113491
- Publication date Apr 23, 2015
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Automatic Generation of Wire Tag Lists for a Metal Stack
- Publication number 20140223397
- Publication date Aug 7, 2014
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Automatic Generation of Wire Tag Lists for a Metal Stack
- Publication number 20140195998
- Publication date Jul 10, 2014
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DETERMINING HIGH QUALITY INITIAL CANDIDATE SINK LOCATIONS FOR ROBUS...
- Publication number 20140181772
- Publication date Jun 26, 2014
- International Business Machines Corporation
- Charles Jay Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRUCTURED PLACEMENT OF LATCHES/FLIP-FLOPS TO MINIMIZE CLOCK POWER...
- Publication number 20140149957
- Publication date May 29, 2014
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIRECT CURRENT CIRCUIT ANALYSIS BASED CLOCK NETWORK DESIGN
- Publication number 20140143746
- Publication date May 22, 2014
- International Business Machines Corporation
- Charles Jay Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EARLY DESIGN CYCLE OPTIMZATION
- Publication number 20140101629
- Publication date Apr 10, 2014
- International Business Machines Corporation
- Charles Jay Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SOLVING TRAFFIC CONGESTION USING VEHICLE GROUPING
- Publication number 20140088791
- Publication date Mar 27, 2014
- International Business Machines Corporation
- Charles Jay Alpert
- G08 - SIGNALLING
Information Patent Application
SOLVING TRAFFIC CONGESTION USING VEHICLE GROUPING
- Publication number 20140081478
- Publication date Mar 20, 2014
- International Business Machines Corporation
- Charles Jay Alpert
- G08 - SIGNALLING
Information Patent Application
SOLVING TRAFFIC CONGESTION USING VEHICLE GROUPING
- Publication number 20140074389
- Publication date Mar 13, 2014
- International Business Machines Corporation
- Charles Jay Alpert
- G08 - SIGNALLING
Information Patent Application
SOLVING NETWORK TRAFFIC CONGESTION USING DEVICE GROUPING
- Publication number 20140071827
- Publication date Mar 13, 2014
- International Business Machines Corporation
- Charles Jay Alpert
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SEPARATE REFINEMENT OF LOCAL WIRELENGTH AND LOCAL MODULE DENSITY IN...
- Publication number 20140007036
- Publication date Jan 2, 2014
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POST-PLACEMENT CELL SHIFTING
- Publication number 20130346938
- Publication date Dec 26, 2013
- International Business Machines Corporation
- Charles J Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ELEMENT PLACEMENT IN CIRCUIT DESIGN BASED ON PREFERRED LOCATION
- Publication number 20130326455
- Publication date Dec 5, 2013
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EARLY DESIGN CYCLE OPTIMZATION
- Publication number 20130326450
- Publication date Dec 5, 2013
- International Business Machines Corporation
- Charles Jay Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESIGNING A ROBUST POWER EFFICIENT CLOCK DISTRIBUTION NETWORK
- Publication number 20130326456
- Publication date Dec 5, 2013
- International Business Machines Corporation
- Charles Jay Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATAPATH PLACEMENT USING TIERED ASSIGNMENT
- Publication number 20130283225
- Publication date Oct 24, 2013
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONGESTION AWARE ROUTING USING RANDOM POINTS
- Publication number 20130272126
- Publication date Oct 17, 2013
- International Business Machines Corporation
- Charles Jay Alpert
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SOLVING CONGESTION USING NET GROUPING
- Publication number 20130275934
- Publication date Oct 17, 2013
- International Business Machines Corporation
- Charles Jay Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COST-EFFECTIVE AND RELIABLE UTILITIES DISTRIBUTION NETWORK
- Publication number 20130096976
- Publication date Apr 18, 2013
- International Business Machines Corporation
- Charles Jay Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-PATTERNING LITHOGRAPHY AWARE CELL PLACEMENT IN INTEGRATED CIR...
- Publication number 20130086543
- Publication date Apr 4, 2013
- International Business Machines Corporation
- Kanak Behari Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Design Routability Using Multiplexer Structures
- Publication number 20130086537
- Publication date Apr 4, 2013
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONSIDERATION OF LOCAL ROUTING AND PIN ACCESS DURING VLSI GLOBAL RO...
- Publication number 20130086544
- Publication date Apr 4, 2013
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING

Charles J. Alpert

Person

Patents Grantslast 30 patents

Post-CTS insertion delay and skew target reformulation of clock tree

Fault-tolerant power-driven synthesis

Waveform propagation timing modeling for circuit design

Power driven synaptic network synthesis

View pruning for routing tree optimization

Systems and methods for routing a clock net with multiple layer ranges

Fault-tolerant power-driven synthesis

Routing topology generation using spine-like tree structure

Region aware clustering

Placement of cells in a multi-level routing tree

Systems and methods for modifying a balanced clock structure

Power-driven synthesis under latency constraints

Systems and methods for clock tree generation with buffers and inve...

Balanced scaled-load clustering

Local cluster refinement

Routing tree topology generation

Systems and methods for assigning clock taps based on timing

Systems and methods for clock tree clustering

Systems and methods for power efficient flop clustering

Clock cell library selection

System and method for constructing spanning trees

Systems and methods for symmetric H-tree construction with complica...

Systems and methods for congestion and routability aware detailed p...

Efficient Ceff model for gate output slew computation in early synt...

Addressing coupled noise-based violations with buffering in a batch...

System and method for evaluating spanning trees

Element placement in circuit design based on preferred location

Solving network traffic congestion using device grouping

Boundary latch and logic placement to satisfy timing constraints

Automatic generation of wire tag lists for a metal stack

Patents Applicationslast 30 patents

FAULT-TOLERANT POWER-DRIVEN SYNTHESIS

Addressing Coupled Noise-Based Violations with Buffering in a Batch...

POWER DRIVEN SYNAPTIC NETWORK SYNTHESIS

POWER-DRIVEN SYNTHESIS UNDER LATENCY CONSTRAINTS

FAULT-TOLERANT POWER-DRIVEN SYNTHESIS

BOUNDARY LATCH AND LOGIC PLACEMENT TO SATISFY TIMING CONSTRAINTS

EFFICIENT CEFF MODEL FOR GATE OUTPUT SLEW COMPUTATION IN EARLY SYNT...

COMPUTER-BASED MODELING OF INTEGRATED CIRCUIT CONGESTION AND WIRE D...

Automatic Generation of Wire Tag Lists for a Metal Stack

Automatic Generation of Wire Tag Lists for a Metal Stack

DETERMINING HIGH QUALITY INITIAL CANDIDATE SINK LOCATIONS FOR ROBUS...

STRUCTURED PLACEMENT OF LATCHES/FLIP-FLOPS TO MINIMIZE CLOCK POWER...

DIRECT CURRENT CIRCUIT ANALYSIS BASED CLOCK NETWORK DESIGN

EARLY DESIGN CYCLE OPTIMZATION

SOLVING TRAFFIC CONGESTION USING VEHICLE GROUPING

SOLVING TRAFFIC CONGESTION USING VEHICLE GROUPING

SOLVING TRAFFIC CONGESTION USING VEHICLE GROUPING

SOLVING NETWORK TRAFFIC CONGESTION USING DEVICE GROUPING

SEPARATE REFINEMENT OF LOCAL WIRELENGTH AND LOCAL MODULE DENSITY IN...

POST-PLACEMENT CELL SHIFTING

ELEMENT PLACEMENT IN CIRCUIT DESIGN BASED ON PREFERRED LOCATION

EARLY DESIGN CYCLE OPTIMZATION

DESIGNING A ROBUST POWER EFFICIENT CLOCK DISTRIBUTION NETWORK

DATAPATH PLACEMENT USING TIERED ASSIGNMENT

CONGESTION AWARE ROUTING USING RANDOM POINTS

SOLVING CONGESTION USING NET GROUPING

COST-EFFECTIVE AND RELIABLE UTILITIES DISTRIBUTION NETWORK

MULTI-PATTERNING LITHOGRAPHY AWARE CELL PLACEMENT IN INTEGRATED CIR...

Design Routability Using Multiplexer Structures

CONSIDERATION OF LOCAL ROUTING AND PIN ACCESS DURING VLSI GLOBAL RO...