Charles P. Geer

Person

Rochester, MN, US

People

Patents Grantslast 30 patents

Information Patent Grant
Level-shifting latch
- Patent number 9,712,170
- Issue date Jul 18, 2017
- International Bueinss Machines Corporation
- Anthony G. Aipperspach
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Level-shifting latch
- Patent number 9,553,584
- Issue date Jan 24, 2017
- International Business Machines Corporation
- Anthony G. Aipperspach
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Architecture for a physical interface of a high speed front side bus
- Patent number 7,945,805
- Issue date May 17, 2011
- International Business Machines Corporation
- Steven John Baumgartner
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Dynamic clock phase alignment between independent clock domains
- Patent number 7,904,741
- Issue date Mar 8, 2011
- International Business Machines Corporation
- Steven John Baumgartner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic clock phase alignment between independent clock domains
- Patent number 7,716,514
- Issue date May 11, 2010
- International Business Machines Corporation
- Steven John Baumgartner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture for a physical interface of a high speed front side bus
- Patent number 7,624,297
- Issue date Nov 24, 2009
- International Business Machines Corporation
- Steven John Baumgartner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase rotator control test scheme
- Patent number 7,573,937
- Issue date Aug 11, 2009
- International Business Machines Corporation
- Steven J. Baumgartner
- G01 - MEASURING TESTING
Information Patent Grant
Latency optimized data alignment racheting scheme
- Patent number 7,558,893
- Issue date Jul 7, 2009
- International Business Machines Corporation
- Charles P. Geer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock frequency detect with programmable jitter tolerance
- Patent number 7,129,757
- Issue date Oct 31, 2006
- International Business Machines Corporation
- Charles Porter Geer
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit test coverage evaluation and adjustment mechanis...
- Patent number 6,212,667
- Issue date Apr 3, 2001
- International Business Machines Corporation
- Charles Porter Geer
- G01 - MEASURING TESTING
Information Patent Grant
Dynamic repair of redundant memory array
- Patent number 6,181,614
- Issue date Jan 30, 2001
- International Business Machines Corporation
- Anthony Gus Aipperspach
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory card resident diagnostic testing
- Patent number 5,274,648
- Issue date Dec 28, 1993
- International Business Machines Corporation
- Richard G. Eikill
- G11 - INFORMATION STORAGE
Information Patent Grant
Fast store-through cache memory
- Patent number 5,206,941
- Issue date Apr 27, 1993
- International Business Machines Corporation
- Richard G. Eikill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory card refresh buffer
- Patent number 5,193,165
- Issue date Mar 9, 1993
- International Business Machines Corporation
- Richard G. Eikill
- G11 - INFORMATION STORAGE
Information Patent Grant
Chip identification method for use with scan design systems and sca...
- Patent number 5,079,725
- Issue date Jan 7, 1992
- IBM Corporation
- Charles P. Geer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for automatically configuring translation of logi...
- Patent number 5,067,105
- Issue date Nov 19, 1991
- International Business Machines Corporation
- John M. Borkenhagen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for compressing and buffering data
- Patent number 4,574,351
- Issue date Mar 4, 1986
- International Business Machines Corporation
- Lam Q. Dang
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
LEVEL-SHIFTING LATCH
- Publication number 20160182052
- Publication date Jun 23, 2016
- International Business Machines Corporation
- Anthony G. Aipperspach
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LEVEL-SHIFTING LATCH
- Publication number 20160182053
- Publication date Jun 23, 2016
- International Business Machines Corporation
- Anthony G. Aipperspach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Architecture for a Physical Interface of a High Speed Front Side Bus
- Publication number 20080147952
- Publication date Jun 19, 2008
- Steven John Baumgartner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Architecture for a Physical Interface of a High Speed Front Side Bus
- Publication number 20080148088
- Publication date Jun 19, 2008
- International Business Machines Corporation
- Steven John Baumgartner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamic Clock Phase Alignment Between Independent Clock Domains
- Publication number 20080126566
- Publication date May 29, 2008
- Steven John Baumgartner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamic Clock Phase Alignment Between Independent Clock Domains
- Publication number 20080072093
- Publication date Mar 20, 2008
- International Business Machines Corporation
- Steven John Baumgartner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Asynchronous Phase Rotator Control
- Publication number 20080069278
- Publication date Mar 20, 2008
- Steven J. Baumgartner
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Phase rotator control test scheme
- Publication number 20060285583
- Publication date Dec 21, 2006
- International Business Machines Corporation
- Steven J. Baumgartner
- G01 - MEASURING TESTING
Information Patent Application
Jitter generator to simulate a closed data eye
- Publication number 20060285584
- Publication date Dec 21, 2006
- International Business Machines Corporation
- Steven J. Baumgartner
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Clock frequency detect with programmable jitter tolerance
- Publication number 20060114032
- Publication date Jun 1, 2006
- International Business Machines Corporation
- Charles Porter Geer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Latency optimized data alignment racheting scheme
- Publication number 20060072619
- Publication date Apr 6, 2006
- International Business Machines Corporation
- Charles P. Geer
- G06 - COMPUTING CALCULATING COUNTING

Charles P. Geer

Person

Patents Grantslast 30 patents

Level-shifting latch

Level-shifting latch

Architecture for a physical interface of a high speed front side bus

Dynamic clock phase alignment between independent clock domains

Dynamic clock phase alignment between independent clock domains

Architecture for a physical interface of a high speed front side bus

Phase rotator control test scheme

Latency optimized data alignment racheting scheme

Clock frequency detect with programmable jitter tolerance

Integrated circuit test coverage evaluation and adjustment mechanis...

Dynamic repair of redundant memory array

Memory card resident diagnostic testing

Fast store-through cache memory

Memory card refresh buffer

Chip identification method for use with scan design systems and sca...

System and method for automatically configuring translation of logi...

Apparatus for compressing and buffering data

Patents Applicationslast 30 patents

LEVEL-SHIFTING LATCH

LEVEL-SHIFTING LATCH

Architecture for a Physical Interface of a High Speed Front Side Bus

Architecture for a Physical Interface of a High Speed Front Side Bus

Dynamic Clock Phase Alignment Between Independent Clock Domains

Dynamic Clock Phase Alignment Between Independent Clock Domains

Asynchronous Phase Rotator Control

Phase rotator control test scheme

Jitter generator to simulate a closed data eye

Clock frequency detect with programmable jitter tolerance

Latency optimized data alignment racheting scheme