Charles W. Selvidge

Person

Charlestown, MA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Reduce/broadcast computation-enabled switching elements in an emula...
- Patent number 11,113,441
- Issue date Sep 7, 2021
- SIEMENS INDUSTRY SOFTWARE INC.
- Charles W Selvidge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bandwidth test in networking System-on-Chip verification
- Patent number 10,664,566
- Issue date May 26, 2020
- Mentor Graphics Corporation
- Suresh Krishnamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Concurrent testbench and software driven verification
- Patent number 10,664,563
- Issue date May 26, 2020
- Mentor Graphics Corporation
- Debdutta Bhattacharya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latency test in networking system-on-chip verification
- Patent number 10,657,217
- Issue date May 19, 2020
- Mentor Graphics Corporation
- Suresh Krishnamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selective conditional stall for hardware-based circuit design verif...
- Patent number 10,579,776
- Issue date Mar 3, 2020
- Mentor Graphics Corporation
- Charles W. Selvidge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Target capture and replay in emulation
- Patent number 10,503,848
- Issue date Dec 10, 2019
- Mentor Graphics Corporation
- Krishnamurthy Suresh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Content addressable memory modeling in emulation and prototyping
- Patent number 10,410,713
- Issue date Sep 10, 2019
- Mentor Graphics Corporation
- Charles W. Selvidge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modeling memory in emulation based on cache
- Patent number 9,898,563
- Issue date Feb 20, 2018
- Mentor Graphics Corporation
- Krishnamurthy Suresh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Target capture and replay in emulation
- Patent number 9,767,237
- Issue date Sep 19, 2017
- Mentor Graphics Corporation
- Krishnamurthy Suresh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Debug environment for a multi user hardware assisted verification s...
- Patent number 9,703,579
- Issue date Jul 11, 2017
- Mentor Graphics Corporation
- Krishnamurthy Suresh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Third party component debugging for integrated circuit design
- Patent number 9,619,600
- Issue date Apr 11, 2017
- Mentor Graphics Corporation
- Charles W. Selvidge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Switching activity reduction through retiming
- Patent number 9,305,126
- Issue date Apr 5, 2016
- Mentor Graphics Corporation
- Charles W. Selvidge
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Adaptive clock management in emulation
- Patent number 9,165,099
- Issue date Oct 20, 2015
- Mentor Graphics Corporation
- Krishnamurthy Suresh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory-based trigger generation scheme in an emulation environment
- Patent number 8,868,974
- Issue date Oct 21, 2014
- Mentor Graphics Corporation
- Gregoire Brunot
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Third party component debugging for integrated circuit design
- Patent number 8,843,861
- Issue date Sep 23, 2014
- Mentor Graphics Corporation
- Charles W. Selvidge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register transfer level design compilation advisor
- Patent number 8,516,411
- Issue date Aug 20, 2013
- Mentor Graphics Corporation
- Sanjay Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Communication scheme between programmable sub-cores in an emulation...
- Patent number 8,352,242
- Issue date Jan 8, 2013
- Mentor Graphics Corporation
- Peer Schmitt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Acyclic modeling of combinational loops
- Patent number 8,181,129
- Issue date May 15, 2012
- Mentor Graphics Corporation
- Amit Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory tracing in an emulation environment
- Patent number 8,108,198
- Issue date Jan 31, 2012
- Mentor Graphics Corporation
- Peer Schmitt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory-based trigger generation scheme in an emulation environment
- Patent number 8,108,729
- Issue date Jan 31, 2012
- Mentor Graphics Corporation
- Gregoire Brunot
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory-based trigger generation scheme in an emulation environment
- Patent number 7,730,353
- Issue date Jun 1, 2010
- Gregoire Brunot
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Software state replay
- Patent number 7,480,610
- Issue date Jan 20, 2009
- Mentor Graphics Corporation
- David C. Scott
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Acyclic modeling of combinational loops
- Patent number 7,454,722
- Issue date Nov 18, 2008
- Mentor Graphics Corporation
- Amit Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Functional verification of logic and memory circuits with multiple...
- Patent number 7,143,377
- Issue date Nov 28, 2006
- Mentor Graphics Corporation
- Muralidhar R. Kudlugi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-synchronized multiplex data transport across synchronous systems
- Patent number 6,961,691
- Issue date Nov 1, 2005
- Mentor Graphics Corporation
- Charles W. Selvidge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Functional verification of logic and memory circuits with multiple...
- Patent number 6,817,001
- Issue date Nov 9, 2004
- Muralidhar R. Kudlugi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic analysis system for logic emulation systems
- Patent number 6,223,148
- Issue date Apr 24, 2001
- Ikos Systems, Inc.
- Kem Stewart
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transition analysis and circuit resynthesis method and device for d...
- Patent number 6,009,531
- Issue date Dec 28, 1999
- Ikos Systems, Inc.
- Charles W. Selvidge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipe lined static router and scheduler for configurable logic syste...
- Patent number 5,850,537
- Issue date Dec 15, 1998
- Virtual Machine Works, Inc.
- Charles W. Selvidge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable multiplexing input/output port
- Patent number 5,847,578
- Issue date Dec 8, 1998
- Virtual Machine Works
- Michael Donald Noakes
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Hybrid Switching Architecture For SerDes Communication Channels In...
- Publication number 20230306169
- Publication date Sep 28, 2023
- Siemens Industry Software Inc.
- Jean-Marc Brault
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ROLLBACK FOR COMMUNICATION LINK ERROR RECOVERY IN EMULATION
- Publication number 20220329351
- Publication date Oct 13, 2022
- Siemens Industry Software Inc.
- Charles W. Selvidge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR MODELING MEMORY DEVICES WITH LATENCY
- Publication number 20220066801
- Publication date Mar 3, 2022
- Siemens Industry Software Inc.
- Charles W. Selvidge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Concurrent Testbench and Software Driven Verification
- Publication number 20180285484
- Publication date Oct 4, 2018
- Mentor Graphics Corporation
- Debdutta Bhattacharya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Latency Test In Networking System-On-Chip Verification
- Publication number 20180113970
- Publication date Apr 26, 2018
- Mentor Graphics Corporation
- Krishnamurthy Suresh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Bandwidth Test In Networking System-On-Chip Verification
- Publication number 20180113961
- Publication date Apr 26, 2018
- Mentor Graphics Corporation
- Krishnamurthy Suresh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEBUG ENVIRONMENT FOR A MULTI USER HARDWARE ASSISTED VERIFICATION S...
- Publication number 20180032357
- Publication date Feb 1, 2018
- Mentor Graphics Corporation
- Krishnamurthy Suresh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Data Injection In Emulation Without Rebooting
- Publication number 20180011956
- Publication date Jan 11, 2018
- Mentor Graphics Corporation
- Ajay Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Target Capture And Replay In Emulation
- Publication number 20170337309
- Publication date Nov 23, 2017
- Mentor Graphics Corporation
- Krishnamurthy Suresh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Modeling Memory In Emulation Based On Cache
- Publication number 20170140083
- Publication date May 18, 2017
- Mentor Graphics Corporation
- Krishnamurthy Suresh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Target Capture And Replay In Emulation
- Publication number 20170140082
- Publication date May 18, 2017
- Mentor Graphics Corporation
- Krishnamurthy Suresh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Switching Activity Reduction Through Retiming
- Publication number 20150269295
- Publication date Sep 24, 2015
- Mentor Graphics Corporation
- Charles W. Selvidge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THIRD PARTY COMPONENT DEBUGGING FOR INTEGRATED CIRCUIT DESIGN
- Publication number 20150149973
- Publication date May 28, 2015
- Mentor Graphics Corporation
- Charles W. Selvidge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Adaptive Clock Management In Emulation
- Publication number 20150100931
- Publication date Apr 9, 2015
- Mentor Graphics Corporation
- Krishnamurthy Suresh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Modeling Content-Addressable Memory For Emulation
- Publication number 20140278329
- Publication date Sep 18, 2014
- Mentor Graphics Corporation
- Charles Selvidge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Partitionless Multi User Support For Hardware Assisted Verification
- Publication number 20140052430
- Publication date Feb 20, 2014
- Mentor Graphics Corporation
- Krishnamurthy Suresh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Partitionless Multi User Support For Hardware Assisted Verification
- Publication number 20140032204
- Publication date Jan 30, 2014
- Mentor Graphics Corporation
- Krishnamurthy Suresh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Third Party Component Debugging For Integrated Circuit Design
- Publication number 20130318484
- Publication date Nov 28, 2013
- Mentor Graphics Corporation
- Charles Selvidge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY-BASED TRIGGER GENERATION SCHEME IN AN EMULATION ENVIRONMENT
- Publication number 20120221316
- Publication date Aug 30, 2012
- Mentor Graphics Corporation
- Gregoire Brunot
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Register Transfer Level Design Compilation Advisor
- Publication number 20120180011
- Publication date Jul 12, 2012
- Sanjay Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY-BASED TRIGGER GENERATION SCHEME IN AN EMULATION ENVIRONMENT
- Publication number 20100223502
- Publication date Sep 2, 2010
- Gregoire Brunot
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Acyclic Modeling of Combinational Loops
- Publication number 20090044157
- Publication date Feb 12, 2009
- Mentor Graphics Corporation
- Amit Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Communication Scheme Between Programmable Sub-Cores in an Emulation...
- Publication number 20080288236
- Publication date Nov 20, 2008
- Peer Schmitt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Tracing in an Emulation Environment
- Publication number 20080288719
- Publication date Nov 20, 2008
- Peer Schmitt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory-based trigger generation scheme in an emulation environment
- Publication number 20070226541
- Publication date Sep 27, 2007
- Gregoire Brunot
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Acyclic modeling of combinational loops
- Publication number 20060123300
- Publication date Jun 8, 2006
- Mentor Graphics Corporation
- Amit Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Software state replay
- Publication number 20060074622
- Publication date Apr 6, 2006
- Mentor Graphics Corp.
- David C. Scott
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Logic analysis system for logic emulation systems
- Publication number 20010010036
- Publication date Jul 26, 2001
- IKOS Systems, Inc.
- Kem Stewart
- G01 - MEASURING TESTING

Charles W. Selvidge

Person

Patents Grantslast 30 patents

Reduce/broadcast computation-enabled switching elements in an emula...

Bandwidth test in networking System-on-Chip verification

Concurrent testbench and software driven verification

Latency test in networking system-on-chip verification

Selective conditional stall for hardware-based circuit design verif...

Target capture and replay in emulation

Content addressable memory modeling in emulation and prototyping

Modeling memory in emulation based on cache

Target capture and replay in emulation

Debug environment for a multi user hardware assisted verification s...

Third party component debugging for integrated circuit design

Switching activity reduction through retiming

Adaptive clock management in emulation

Memory-based trigger generation scheme in an emulation environment

Third party component debugging for integrated circuit design

Register transfer level design compilation advisor

Communication scheme between programmable sub-cores in an emulation...

Acyclic modeling of combinational loops

Memory tracing in an emulation environment

Memory-based trigger generation scheme in an emulation environment

Memory-based trigger generation scheme in an emulation environment

Software state replay

Acyclic modeling of combinational loops

Functional verification of logic and memory circuits with multiple...

Non-synchronized multiplex data transport across synchronous systems

Functional verification of logic and memory circuits with multiple...

Logic analysis system for logic emulation systems

Transition analysis and circuit resynthesis method and device for d...

Pipe lined static router and scheduler for configurable logic syste...

Programmable multiplexing input/output port

Patents Applicationslast 30 patents

Hybrid Switching Architecture For SerDes Communication Channels In...

ROLLBACK FOR COMMUNICATION LINK ERROR RECOVERY IN EMULATION

SYSTEM AND METHOD FOR MODELING MEMORY DEVICES WITH LATENCY

Concurrent Testbench and Software Driven Verification

Latency Test In Networking System-On-Chip Verification

Bandwidth Test In Networking System-On-Chip Verification

DEBUG ENVIRONMENT FOR A MULTI USER HARDWARE ASSISTED VERIFICATION S...

Data Injection In Emulation Without Rebooting

Target Capture And Replay In Emulation

Modeling Memory In Emulation Based On Cache

Target Capture And Replay In Emulation

Switching Activity Reduction Through Retiming

THIRD PARTY COMPONENT DEBUGGING FOR INTEGRATED CIRCUIT DESIGN

Adaptive Clock Management In Emulation

Modeling Content-Addressable Memory For Emulation

Partitionless Multi User Support For Hardware Assisted Verification

Partitionless Multi User Support For Hardware Assisted Verification

Third Party Component Debugging For Integrated Circuit Design

MEMORY-BASED TRIGGER GENERATION SCHEME IN AN EMULATION ENVIRONMENT

Register Transfer Level Design Compilation Advisor

MEMORY-BASED TRIGGER GENERATION SCHEME IN AN EMULATION ENVIRONMENT

Acyclic Modeling of Combinational Loops

Communication Scheme Between Programmable Sub-Cores in an Emulation...

Memory Tracing in an Emulation Environment

Memory-based trigger generation scheme in an emulation environment

Acyclic modeling of combinational loops

Software state replay

Logic analysis system for logic emulation systems